200 nm Wafer-to-wafer overlay accuracy in wafer level Cu/SiO2 hybrid bonding for BSI CIS

Abstract

Sub 200 nm wafer-to-wafer (w2w) overlay accuracy on the entire 300 mm wafer was successfully demonstrated via wafer level Cu/SiO 2 hybrid bonding. Cu bonding pads relevant for back-side illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS) were used for the experiment. Further, a crucial component to improve the overlay accuracy, namely the overlay model which identifies systematic alignment errors, was described. IntroductionThe growing demand for increased functionality and higher performance in integrated circuits (ICs) requires more transistors which means the transistor and interconnect size must decrease in order to maintain the same chip size (with respect to its lateral dimensions). Because of these factors different integration schemes like three-dimensional (3D) ICs with the purpose of reducing global interconnection length become more and more relevant for increased speed and operation frequency. W2w bonding is an attractive and crucial technique for enabling 3D integration. The bonding processes of fusion bonding and metal bonding, such as metal thermocompression, eutectic, and transient liquid phase (TLP) bonding, are well established and many of them are already in mass production [1][2][3][4]. The more recent approach of hybrid wafer level bonding is an attractive technique for reliably connecting heterogeneous structures, such as connecting processor with memory, analogue IC or microelectromechanical systems (MEMS), having high-density interconnects (<10 μm pitch). Within this work the bonding process for Cu/SiO 2 hybrid structures, which is an attractive material combination for BSI CIS, was investigated [5]. Furthermore, relevant changes to improve the w2w post-bond overlay accuracy are presented, as well as the overlay model which was introduced to isolate and quantify different global misalignment root causes, such as translation, rotation and scaling.

Magnetic alignment technology for wafer bonding

“…The bumps and pads on the wafer are constantly shrinking, and the alignment requirements are getting higher and higher. In the wafer-level hybrid bonding process, less 200 nm of wafer alignment is required (Rebhan et al , 2015). The interconnection copper pillar pitch of 300 mm wafer hybrid bonding will scale down to 1.8 μm or even lower (Kim et al , 2016; Oprins et al , 2016).…”

Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application

“…On the other hand, roomtemperature bonding with post-annealing requires lower surface roughness and highly hydrophilic surfaces but allows for batch annealing after bonding, leading to significantly higher throughput. Furthermore, owing to its ability to achieve highly accurate alignment through its spontaneous bonding properties, this technique has established itself as a major bonding technique in advanced packaging [8]. In light of the above, room-temperature bonding with post-annealing technology has been extensively adopted in the industry due to these advantages.…”

Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding

“…Although low temperature hybrid bonding has been applied extensively to wafer-to-wafer (W2W) bonding, [10][11][12] especially in the field of CMOS image sensors (CIS), 13,14 the detailed thermomechanics has not been studied extensively. In this paper, we focus on D2W hybrid bonding for two reasons: heterogeneous integration via dielets or chiplets is catching attraction in the implementation of high-performance systems; and at the individual contact level, there is no significant difference between die-to-die, die-to-wafer or for that matter wafer-to-wafer hybrid bonding.…”