Abstract-Increasing chip power densities allied to the continuous technology shrink is making emerging multiprocessor embedded systems more vulnerable to soft errors. Due the high cost and design time inherent to board-based fault injection approaches, more appropriate and efficient simulation-based fault injection frameworks become crucial to guarantee the adequate design exploration support at early design phase. In this scenario, this paper proposes a fast and flexible fault injector framework, called OVPSim-FIM, which supports parallel simulation to boost up the fault injection process. Aiming at validating OVPSim-FIM, several fault injection campaigns were performed in ARM processors, considering a market leading RTOS and benchmarks with up to 10 billions of object code instructions. Results have shown that OVPSim-FIM enables to inject faults at speed of up to 10,000 MIPS, depending on the processor and the benchmark profile, enabling to identify erros and exceptions according to different criteria and classifications.

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Virtual platform frameworks have been extended to allow earlier soft error analysis of more realistic multicore systems (i.e., real software stacks, state-of-the-art ISAs). The high observability and simulation performance of underlying frameworks enable to generate and collect more error/failurerelated data, considering complex software stack configurations, in a reasonable time. When dealing with sizeable failure-related data sets obtained from multiple fault campaigns, it is essential to filter out parameters (i.e., features) without a direct relationship with the system soft error analysis. In this regard, this paper proposes the use of supervised and unsupervised machine learning techniques, aiming to eliminate non-relevant information as well as identify the correlation between fault injection results and application and platform characteristics. This novel approach provides engineers with appropriate means that able are able to investigate new and more efficient fault mitigation techniques. The underlying approach is validated with an extensive data set gathered from more than 1.2 million fault injections, comprising several benchmarks, a Linux OS and parallelization libraries (e.g., MPI, OpenMP), as well as through a realistic automotive case study.

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ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.

The growing concerns of energy efficiency and performance scalability motivate research in the area of manycore embedded systems. The software development of such systems plays an important role on the system performance, while accounting for a significant part of the total energy consumption. Thus, it becomes imperative to consider the software energy consumption at early stages of the software development. This paper proposes an instruction-driven energy analysis approach that provides an accurate and practical way of evaluating software energy cost at the speed of up to 1.8 MIPS. Results show that the accuracy of our approach varies from 0.06% to 8.05% when compared to a gate-level implementation.Keywords -Instruction-driven energy model, fast and accurate energy evaluation, JIT-based simulation, OVP.

To take advantage of the performance enhancements provided by multicore processors, new instruction set architectures (ISAs) and parallel programming libraries have been investigated across multiple industrial segments. It is investigated the impact of parallelization libraries and distinct ISAs on the soft error reliability of two multicore ARM processor models (i.e., Cortex-A9 and Cortex-A72), running Linux Kernel and benchmarks with up to 87 billion instructions. An extensive soft error evaluation with more than 1.2 million simulation hours, considering ARMv7 and ARMv8 ISAs and the NAS Parallel Benchmark (NPB) suite is presented.