Fast energy evaluation of embedded applications for many-core systems

Abstract

The growing concerns of energy efficiency and performance scalability motivate research in the area of manycore embedded systems. The software development of such systems plays an important role on the system performance, while accounting for a significant part of the total energy consumption. Thus, it becomes imperative to consider the software energy consumption at early stages of the software development. This paper proposes an instruction-driven energy analysis approach that provides an accurate and practical way of evaluating software energy cost at the speed of up to 1.8 MIPS. Results show that the accuracy of our approach varies from 0.06% to 8.05% when compared to a gate-level implementation.Keywords -Instruction-driven energy model, fast and accurate energy evaluation, JIT-based simulation, OVP.

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

“…Authors in [14] present a fast energy evaluation of embedded applications for many-core systems. They use OVP to feed an instruction-driven energy model.…”

“…Like in [14] also this tool consists of the same two parts. The power model development and the system-level simulator with the power estimator kernel.…”

Hierarchical energy monitoring for task mapping in many-core systems

“…The processor EC related to the execution of a given task is a function of the number of executed instructions. In our model, the energy cost of each instruction is determined from a gate-level implementation of the processor, as proposed by Rosa et al [36].…”

“…The set of classes is defined as C = {c 0, c 2, … ,c 8 }, with 9 different classes (e.g. arithmetic, logic, branch) [36]. Results show that the error of adopted instruction analyzer module varies from 0.06% to 8.05% when compared to a gate-level implementation [36].…”

“…arithmetic, logic, branch) [36]. Results show that the error of adopted instruction analyzer module varies from 0.06% to 8.05% when compared to a gate-level implementation [36]. The instruction analyzer module corresponds to nine instruction counters, included in the control part of the processor.…”