This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under high dv/dt. This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positive dv/dt and negative dv/dt are investigated. Analysis results show that the high dv/dt with long duration caused by high voltage SiC MOSFETs' switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positive dv/dt, extremely small parasitic capacitances (<0.01 pF) between the drain terminal and protection circuitry could still compromise noise immunity of the desat protection circuitry that has a high-impedance voltage divider. Comprehensive design guidelines are summarized to boost the noise immunity, including circuit design, component selection, and PCB layout. The noise immunity margin under the positive dv/dt is also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.
In power systems with grid-forming inverters (GFMs), small-signal instability issues could occur due to harmonic excitation, impedance interactions, and poor inverter control design. There mainly exist two types of stability issues based on the frequency range. One is the low-frequency resonance (0 -2f 0 Hz) and the other is the high-frequency harmonics (above 2f 0 Hz), where f 0 is the system fundamental frequency. By assuming that the low-frequency related controls are well designed, this paper addresses the high-frequency harmonic issues. The goal is to develop a system stabilization function (SSF) to eliminate any high-frequency stability issues under various grid conditions without affecting predefined low-frequency behaviors. The idea is to conduct the inverter passivation test at the system harmonic resonant frequency so that the corresponding harmonic instability can be removed. To achieve this, the resonant frequency of the harmonic instability is detected first, and then if the magnitude of the resonant component exceeds the threshold value, the proposed SSF will be enabled, thus the system would be stabilized. Both simulation and experimental tests are conducted to validate the effectiveness of the proposed approach.INDEX TERMS Grid-forming inverters, harmonic instability, online harmonic detection, passivity-based design.
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