A water-based route has been demonstrated for synthesizing ZnSe and Cd-doped ZnSe (Zn(x)Cd(1-x)Se, 0 < x < 1) quantum dots (QDs) that have tunable and narrow photoluminescence (PL) peaks from the ultraviolet A (UVA) to the blue range (350-490 nm) with full-width at half-maximum (fwhm) values of 24-36 nm. Hydrazine (N(2)H(4)) was used to maintain oxygen-free conditions, allowing the reaction vessel to be open to air. The properties of the QDs were controlled using the thiol ligands, 3-mercaptopropionic acid (MPA), thiolglycolic acid (TGA), and l-glutathione (GSH). On the basis of optical spectra, linear three-carbon MPA attenuated nucleation and growth, yielding small ZnSe QDs with a high density of surface defects. In contrast, TGA and GSH produced larger ZnSe QDs with lower surface defect densities. The absorption spectra show that growth was more uniform and better controlled with linear two-carbon TGA than branched bifunctional GSH. After 20 min of growth TGA-capped ZnSe had an average diameter of 2.5 nm based on high-resolution transmission electron microscopy images; these nanocrystals had an absorbance peak maximum of approximately 340 nm (3.65 eV) and a band gap PL emission peak at 372 nm (3.34 eV). Highly fluorescent Zn(x)Cd(1-x)Se QDs were fabricated by adding a Cd-thiol complex directly to ZnSe QD solutions; PL peaks were tuned in the blue range (400-490 nm) by changing the Zn to Cd ratio. The Cd-bearing nanocrystals contained proportionally more Se based on X-ray photoelectron spectroscopy, and Cd-Se bonds had ionic character, in contrast to primarily covalent Zn-Se bonds.
We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4-µm pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum Manuscript
Hardware acceleration of deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, high accuracy Multiply-ACcumulate (MAC) operations, and routing frameworks for implementing arbitrary deep neural network (DNN) topologies. In this article, we present a 14-nm test-chip for Analog AI inference-it contains multiple arrays of phase change memory (PCM)devices, each array capable of storing 512 × 512 unique DNN weights and executing massively parallel MAC operations at the location of the data. DNN excitations are transported across the chip using a duration representation on a parallel and reconfigurable 2-D mesh. To accurately transfer inference models to the chip, we describe a closed-loop tuning (CLT) algorithm that programs the four PCM conductances in each weight, achieving <3% average weighterror. A row-wise programming scheme and associated circuitry allow us to execute CLT on up to 512 weights concurrently. We show that the test chip can achieve near-software-equivalent accuracy on two different DNNs. We demonstrate tile-to-tile transport with a fully-on-chip two-layer network for MNIST (accuracy degradation ∼0.6%)
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