The EDA design flows must be retooled to cope with the rapid increase in the number of operational modes and process corners for a VLSI circuit, which in turn results in different and sometimes conflicting design goals and requirements. Single-objective solutions to various design optimization problems, ranging from sizing and fanout optimization to technology mapping and cell placement, must hence be augmented to deal with this changing landscape. This paper starts off by presenting a variety of methods for providing analytical models for power and delay to be used in the optimization algorithms. The modeling includes non-convex and convex functional forms. Next, a class of robust and scalable methods for solving multi-objective optimization problems (MOP) in a digital circuit is presented. We present the results of a multiobjective (i.e., power dissipation and delay) gate (transistor) sizing optimization algorithm to demonstrate the effectiveness of our method. We set up the problem as a simultaneous, multi-objective optimization problem and solve it by using the Weighted Sum and Compromise Programming methods. After comparing these two methods, we present the Satisficing Trade-off Method (STOM) to find the most desirable operating point of a circuit.
In this paper a pipelined 16x16+32 MAC structure is explained. This is a fused MAC which is using modified Booth encoding technique and a new low-voltage-swing 4:2 compressor. For the final adder, it is using low-voltage-swing carry-select structure. With this topology, we achieved a 5-stage pipelined MAC with 10GHz clock frequency and 15mW/GHz average power dissipation in 65nm CMOS technology with 1.2V power supply.
In this paper we propose a fast and efficient method of multiobjective optimization for 3DIC building block placement. The objectives are cost, performance and thermal reliability. Our proposed method is based on a Quasi-Newton analytical optimization method. Our approach also uses a scalarization method of Compromise Programming, in which the weighted distance of the objectives from their minimum points is optimized. A fast 3DIC thermal map model is used in the optimization algorithm to eliminate the thermal analysis bottleneck during the optimization iterations. In comparison with previous multiobjective optimizations for sample 3DIC configurations, our method reduces the peak temperature by 4.3% and total wire length by 5.7% while it is more than 17x faster in the optimization runtime, on average.
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