Implementation of a High-Speed Low-Power 32-Bit Adder in 7Onm Technology

Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology

“…The FCSL and Sparse-Tree adders are also compared with the Low-Voltage Swing adder structure [6] regarding speed and power and the results are summarized in Table IV.…”

15GHz low-voltage-swing carry-lookahead adder

“…We compared our design with three previous high speed 32-bit adders [2,3,4]. We implemented these adders in 65 nm technology with 1.3 V voltage supply and compared them with our proposed adder in Table I.…”

“…These adders are guaranteed to accommodate the shown frequency at all process corners. The LVS-CLA adder is 20% faster than LVS carry-select adder [2] with 52% less power dissipation. This achieved for usage of fewer transistors used in the main circuits of the LVS-CLA adder.…”

“…Our proposed tree has the advantage of using LVS signals in the internal nodes, and this will reduce propagation delay significantly. In comparison with 32-bit LVS carry-select adder with blocks of 16-bit carry skip adders, in which there is a successive carry generation [2], as the proposed adder has a CLA structure, parallel carry generation is fulfilled. Every forth bit can independently generate its carry-out.…”

“…Low-voltage-swing topologies [1,2] and carrylookahead structures with sparse tree carry-generate circuits [3,4] are two important techniques used in the latest high speed adders.…”