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International audienceThis paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework is the one of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it is shown to provide a unified approach for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for WiMAX irregular LDPC codes and we show they provide different trade-offs between hardware complexity and decoding performance. In particular, we derive a set of 27 NS-FAIDs that provide decoding gains up to 0.36 dB, while yielding a memory / interconnect reduction up to 25% / 30% compared to the Min-Sum decoder

Abstract-This paper introduces a new approach to costeffective, high-throughput hardware designs for Low Density Parity Check (LDPC) decoders. The proposed approach, called Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different trade-offs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.

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