Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Abstract

Abstract-This paper introduces a new approach to costeffective, high-throughput hardware designs for Low Density Parity Check (LDPC) decoders. The proposed approach, called Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different trade-offs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.

Optimization of Sign-Preserving Noise-Aided Min-Sum Decoders with Density Evolution

“…It can also be observed that, to the best authors knowledge, all paper on finite precision use the "no-decision value", i.e., a Log-Likelihood Ratio (LLR) equal to 0 (without defined sign, thus) in their messages representation. This is also true for the recent work on Non-surjective Finite Alphabet Iterative Decoders (NS-FAIDs) [7] which provides a unified framework for several MS-based decoders like Normalized MS (NMS) decoder, OMS decoder, Partially OMS decoder. In [8], the authors have shown that 3 or 4 bits quantized decoder can benefit from the introduction of particular randomness applied in the amplitude of messages during the decoding process.…”

“…where ξ = 1 + ((d v + 1) mod 2) where d v is the degree of the VN v. Note that the other values of ξ give worse decoding performance. From (7), one can note that, by construction, µ…”

Finite Alphabet Iterative Decoding of LDPC Codes with Coarsely Quantized Neural Networks

“…We remark that different techniques such as Non-Surjective FAID [17] and Information bottleneck [18] can be used to design Q msg , but these alternative approaches are beyond the scope of this paper.…”

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

“…In a hardware implemented LDPC decoder, the maximal operating frequency is limited by the length of the longest data path (and so-called, critical path) and f max should be inferior to 1/t D , (f max < 1/t D ), where t D is the length of the critical path to avoid the timing error in run-time [25]. In order to improve the decoding throughput (assuming keeping N , It ave and N c constant), the hardware implementations of LDPC decoders tend to be parallelized to shorten the critical path [22], increasing maximally the achievable operating frequency f max . However, the maximization of the operating frequency in some BF decoders reported in the literature, such as GDBF, PGDBF [14] or MBF [11] may be limited since the global operation still required in these decoders, dramatically increases the critical path [17].…”

“…, code rate R = 0.50 regular LDPC code [22] (denoted as dv3R050N1296) show that, the MF occupies more than 40% of the total length of the critical path (the details of synthesis setup are introduced in section V). The MF is also a large part of PGDBF in terms of complexity since it requires approximately N − 1 CASUs.…”