Abstract:The NoC paradigm is one, if not the only one, fit to enable the integration of an exceedingly large number of computational, logical and storage blocks in a single chip. This paper presents a novel technique called CGMAP, which finds a mapping of the vertices of a task graph to the tiles of a mesh based NoC architecture. The proposed algorithm is basically a genetic algorithm, which takes the advantages of the chaotic systems by using them instead of the random processes in the GA. Experimental results show that the proposed algorithm performs as well as the previously proposed mapping algorithms considering some performance indexes such as hop distance, energy consumption, and latency ratio.
The NoC paradigm is one, if not only one, fit to enable the integration of an exceedingly large number of computational, logical and storage blocks in a single chip. The paper presents a novel technique called CGMAP, which finds a mapping of the vertices of a task graph to the tiles of a mesh based NoC architecture, with an objective of improving the Quality of Service (QoS) in networks-on-Chip. The proposed algorithm is basically a genetic algorithm, which takes the advantage of the chaotic systems by using them instead of the random processes used in the GA. Different one-dimensional chaotic maps are introduced and applied to the proposed algorithm in order to compare the performance of each map in finding the best solution for the NoC mapping problem. The results confirm an increase in some performance indexes, due to chaotic sequences. have been proposed to support the trend for Systems-on-Chip integration. NoCs are well poised to realize the communication infrastructure for SoCs with tens or hundreds of computational cores, where parallel processing creates a significant traffic that needs to be managed with run-time techniques [1].
International Conference on Computational Science and Engineering978-0-7695-3823-5/09 $26.00
Abstract:Mapping is one of the most critical issues in designing a NoC-based system. A good mapping of an application to a NoC will lead to more traffic among resources, which are physically close on the chip. In this paper, we introduce several one-dimensional chaotic maps for solving the NoC mapping problem. In addition we compare the solution qualities in accordance with different criteria mainly communication cost and convergence time. The results confirm an increase, due to chaotic sequences, in the value of some performance indexes. Keywords: network-on-chip, mapping, chaotic maps Classification: Integrated circuits
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