Evaluating the Performance of a Chaos Genetic Algorithm for Solving the Network on Chip Mapping Problem

Abstract

The NoC paradigm is one, if not only one, fit to enable the integration of an exceedingly large number of computational, logical and storage blocks in a single chip. The paper presents a novel technique called CGMAP, which finds a mapping of the vertices of a task graph to the tiles of a mesh based NoC architecture, with an objective of improving the Quality of Service (QoS) in networks-on-Chip. The proposed algorithm is basically a genetic algorithm, which takes the advantage of the chaotic systems by using them instead of the random processes used in the GA. Different one-dimensional chaotic maps are introduced and applied to the proposed algorithm in order to compare the performance of each map in finding the best solution for the NoC mapping problem. The results confirm an increase in some performance indexes, due to chaotic sequences. have been proposed to support the trend for Systems-on-Chip integration. NoCs are well poised to realize the communication infrastructure for SoCs with tens or hundreds of computational cores, where parallel processing creates a significant traffic that needs to be managed with run-time techniques [1]. International Conference on Computational Science and Engineering978-0-7695-3823-5/09 $26.00

Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip

“…In this section, we implement the simulation on three randomly generated benchmarks of a varied number of IP cores [15] and a well known application, namely Video Object Plane Decoder (VOPD) with 16 IP cores [11], [16]. The evaluated chip architecture is mesh-based.…”

“…Step 5: Local search for every chromosome of the next generation with the simulated annealing approach to get better solution [11].…”

“…Moreover, the local interconnections between resources and switches are independent of the size of the network in mesh topology [11]. So we focus on mesh topology architecture and assume all PEs have the same size in this paper.…”

“…So we focus on mesh topology architecture and assume all PEs have the same size in this paper. The design flow for NoC architecture involves the following three steps [11]. First, analyze the traffic characteristics of an application to obtain a task graph and then convert it into a set of concurrent communicating tasks.…”

“…This algorithm has been implemented and evaluated on three randomly generated benchmarks of a varied number of IP cores [15] and a well known application, namely Video Object Plane Decoder (VOPD) with 16 IP cores [11], [16]. And then, we compare the simulation results among PHA and some previous mapping algorithms such as MOGA [15] and TGA [17].…”