This paper presents a High Dynamic Range (HDR) image sensor architecture that uses capabilities of threedimensional integrated circuit (3D IC) to reach a dynamic range over 120 dB without modifying the classic (3T or 4T) pixel architecture. The integration time is evaluated on subsets of pixels on the lower IC of the stack and then sent back by vertical interconnections to the sensor array.

In this paper, the potential benefits of image sensor three-Dimensional integration are evaluated. A case study on a High Dynamic Range (HDR) image sensor is done with performance comparison of the architecture developed for the 3D technology and the one used for the 2D integration. It specifically focuses on the power consumption where it shows that the 3D architecture can bring a decrease of the power consumption of a factor of at least 2.5 while keeping the same image sensor performances and even improving image quality.

High Dynamic Range (HDR) Image sensors aim at having a dynamic over 120dB. Compared to classical architectures this is obtained at the cost of a higher transistor count, thus lower fill factor. Three Dimensional integrated circuits (3D-IC) somehow change the constraints, photodiodes and electronics can be stacked on different layers, giving more processing powers without compromising the fill factor.In this paper, we propose an original architecture for a high dynamic 3D image sensor with data reduction obtained by local compression. HDR acquisition is based on a floating point coding shared by a group of pixel (macro-pixel), thus giving also a first level of compression. A second level of compression is performed by using a Discrete Cosine Transform (DCT). With this new concept a good image quality (PSNR of about 40 dB) and a high dynamic range (120 dB) are obtained within a pixel area of 5µm×5µm.