A novel 3D architecture for high-dynamic range image sensor and on-chip data compression

Abstract

High Dynamic Range (HDR) Image sensors aim at having a dynamic over 120dB. Compared to classical architectures this is obtained at the cost of a higher transistor count, thus lower fill factor. Three Dimensional integrated circuits (3D-IC) somehow change the constraints, photodiodes and electronics can be stacked on different layers, giving more processing powers without compromising the fill factor.In this paper, we propose an original architecture for a high dynamic 3D image sensor with data reduction obtained by local compression. HDR acquisition is based on a floating point coding shared by a group of pixel (macro-pixel), thus giving also a first level of compression. A second level of compression is performed by using a Discrete Cosine Transform (DCT). With this new concept a good image quality (PSNR of about 40 dB) and a high dynamic range (120 dB) are obtained within a pixel area of 5µm×5µm.