The processing and design geometric scaling effects on t h e s o f t -e r r o r t o l e r a n c e l e v e l s of t h e 16K 2-pm technology and t h e 256K 1-pm technology CMOS SRAMs are separated by f a b r i c a t i n g t h e 16K 2-pm d e s i g n w i t h t h e 1-pm process. Although the 1-pm twin-tub process is inherently more t o l e r a n t t h a n t h e p-well p r o c e s s t o s o f t e r r o r s , t h e densely packed 1-pm memory c e l l s become v e r y s o f t b e c a u s e o f t h e dominant e f f e c t of the channel w i d t h reduction. An advanced device-plus-circuit simulator was used to c a l c u l a t e t h e d i f f e r e n t i a l c o n t r i b u t i o n from each o f t h e v e r t i c a l a n d l a t e r a l d i m e n s i o n a l c h a n g e s i n v o l v e d i n t h e t e c h n o l o g y t r a n s i t i o n . Good a g r e e m e n t b e t w e e n t h e s i m u l a t i o n s a n d t h e experimental data is reached by p r o p e r l y c o r r e c t i n g t h e 2D m o d e l t o a c c o u n t f o r t h e p h e n o m e n a l saturation effect involving very heavy ions.
The reliability of Integrated Injection Logic (I2L) or Merged Transistor Logic (MTt) circuits fabricated in a standard bipolar technology with Ti-Pt-Au interconnection is reported. The study is based on accelerated stress aging and actual field results.Experiments are described which demonstrate that I2L circuit failure in humid ambients due to Au electrolysis will not occur because of low voltage operation. Failure rates less than 10 FITs for an LSI part (.001% failure per 1000 device hours) under normal stress over a 40 year life are predicted for the main population by accelerated bias temperature and bias humidity stress. Well behaved current gain (eu) under bias temperature step stress indicates that Ou degradation will not be a significant failure mechanism.At this writing, more than 60 million device hours have been accumulated for LSI chips in specific applications with no reported chip failures. This field result firmly supports accelerated stress reliability predictions.
The monolithic integration of MicroElectroMechanical Systems (MEMS) with the driving, controlling, and signal processing electronics promises to improve the performance of micromechanical devices as well as lower their manufacturing, packaging, and instrumentation costs. Key to this integration is the proper interleaving, combining, and customizing of the manufacturing processes to produce functional integrated micromechanical devices with electronics.We have developed a MEMS-first monolothic integrated process that first seals the micromechanical devices in a planarized trench and then builds the electronics in a conventional CMOS process.To date, most of the research published on this technology has focused on the performance characteristics of the mechanical portion of the devices, with little information on the attributes of the accompanying electronics. This work attempts to reduce this information void by presenting the results of SPICE Level 3 and BSIM3v3.1 model parameters extracted for the CMOS portion of the MEMS-first process. Transistor-level simulations of MOSFET current, capacitance, output resistance, and transconductance versus voltage using the extracted model parameters closely match the measured data. Moreover, in model validation efforts, circuit-level simulation values for the average gate propagation delay in a 101-stage ring oscillator are within 13-18% of the measured data. In general, the BSIM3v3.1 models provide improved accuracy over the SPICE Level 3 models. These results establish the following: (1) the MEMS-first approach produces functional CMOS devices integrated on a sbgle chip with MEMS devices and (2) the devices manufactured in the approach have excellent transistor characteristics. Thus, the MEMS-first approach renders a solid technology foundation for customers designing in the technology.
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