Single Event Upset Immune Integrated Circuits for Project Galileo

Giddings, A. E.; Hewlett, F.W.; Treece, R.K.; Nichols, Donald K.; Smith, L. S.; Zoutendyk, J. A.

doi:10.1109/tns.1985.4334086

Cited by 18 publications

(6 citation statements)

References 4 publications

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“…Methods for hardening ICs to SEU were widely developed and used throughout this decade [11], [12]. At the same time, research into the fundamental mechanisms behind SEEs was paying dividends in increased scientific understanding of the problem.…”

Section: See: a Brief Historymentioning

confidence: 99%

“…For example, if the current is based on device simulations of a struck, unloaded device [152], then the circuit simulation inherits the inaccuracy of the improperly loaded device simulation. Still, circuit simulations have provided considerable insight into SEU in memories and have resulted in improvements to hardening techniques for a variety of circuits [12], [87], [103], [153], [154].…”

Section: Mixed Device/circuit Simulationsmentioning

confidence: 99%

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Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

894

427

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Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

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Section: See: a Brief Historymentioning

confidence: 99%

Section: Mixed Device/circuit Simulationsmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

894

427

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“…SEUs occur when a high energy ion (from a cosmic ray or solar flare) or energetic proton (from the trapped radiation belts) penetrates a semiconductor device ( Figure 4.13). There are several upset mechanisms [3,[176][177][178][179][180][181][182][183][184][185][186][187][188][189]: (1) Direct ionization of the semiconductor; (2) Ionization by recoil nuclei and alpha particles from nuclear reactions;…”

Section: Discussion Of Interactionmentioning

confidence: 99%

Environmental Interactions Technology Status

Stevens¹,

Kirkpatrick²,

Chaky³

et al. 1986

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“…Towards the early 1980s, SEU became a serious research topic in the radiation-effect scientific community. The primary research during that period was mostly focussed on Dynamic RAMs, SRAMs and their involvement with latches and flip-flops [19,20]. During the late 1980s, studies based on SEEs has been done in complex logic circuits [20,21,22].…”

Section: Figure 2 Radiation In Terrestrial and Space Environmentsmentioning

confidence: 99%

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

Sengupta,

Yadav

2024

Preprint

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In memory, single event upset (SEU) and single event multiple node upset (SEMNU) have become the principal problems during the past four decades. Significant dependability issues arise from these upsets in a variety of applications such as space, terrestrial, military, and healthcare sector. The use of scaled on-chip memory devices to store private and sensitive data has grown dramatically in the last several years across all the sectors. Memory devices are seriously at risk from non-invasive side-channel assaults (SCAs), which extract secret and sensitive information as well as during SEU/SEMNU, which may flip stored secret and sensitive information. This article presents the history behind the emergence of radiation-hardened circuits and survey of several techniques to mitigate the impact of radiation over the past few decades along with SCA based on leakage power analysis. By educating the researchers on two crucial on-chip memory issues—radiation effect SEU/SEMNU and SCA—this work seeks to accelerate co-design efforts.

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Single Event Upset Immune Integrated Circuits for Project Galileo

Cited by 18 publications

References 4 publications

Basic mechanisms and modeling of single-event upset in digital microelectronics

Basic mechanisms and modeling of single-event upset in digital microelectronics

Environmental Interactions Technology Status

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

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