In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm 2 .The chip is divided into four 8Gb arrays. Each array consists of 684 blocks and each block consists of 384 pages. The page size is 4KB that can be extended to 16KB in quad-plane operation. The chips main features are summarized in Fig. 24.7.1.A technique called source-bias read/verify, consisting in raising the source voltage during read, is been implemented to widen the V T allocation window. A new sensing technique is adopted to ensure that the BL-to-source-voltage difference remains constant as the source voltage is raised during read. The LMU technique, consisting in programming lower (L), middle (M) and upper (U) pages in consecutive order, as shown in Fig. 24.7.2, is adopted to improve the precision of distribution placement by mitigating the floating-gate interference (FG-FG) [5]. The first pulse ramp technique [6][7], consisting in shaping the first program and erase pulse with an initial voltage ramp, is implemented to better preserve oxide integrity and, therefore, data retention. The final distributions achieved with all the above-mentioned techniques are shown in Fig 24.7.3.The chip supports asynchronous data I/O at 20ns cycle time and synchronous DDR access at an I/O rate of 6ns/byte. This read performance is achieved by using the data path architecture shown in Fig. 24.7.4. The architecture is based on the following key design points: four bytes simultaneous sensing in a plane, three stages pipeline and byte mux at I/O pads level. The first stage pipe is to account for RE# and column-address counter propagation; the second stage pipe is to account for address decoder, cache selection and second sensing (SSA) propagation; the third stage pipe is to account for plane mux and data propagation. Multi-plane operations are supported up to a maximum of four planes.The analog system features 10-bit resolution. A digital thermometer is developed for on-chip temperature compensation of array operation. Most of the 3b/c related features are implemented by enhancing the controllability of the analog block by the chip controller via dedicated control registers and by performing all accurate analog operations in precision low-voltage low-noise analog-signal-level (ASL) circuitry built around a 10-bit resistor ladder, as shown in Fig. 24.7.5. In this ap...
NAND flash has been steadily growing in popularity among different applications such as SSD, hybrid HDD, and game consoles; and new applications are emerging that require higher read/write performance. A 3.3V 8Gb NAND Flash memory with a synchronous double-data-rate (DDR) interface is designed and fabricated using 3M 50nm technology to meet the requirements of these markets. We achieve a NAND Flash program throughput of 100MB/s with quad-plane operation, which is 5× previously reported [1,2]. I/O read/write throughput of 200MB/s is achieved using a newly developed DDR interface [3] and data path [4]. The chip features a dual interface, supporting both the newly developed synchronous DDR interface as well as the standard, asynchronous NAND Flash interface. A 64-cell string [5] is adopted to reduce the effective cell size, including the select transistors, to 0.011µm 2 and reduce the die size to 169.5mm 2 . Figure 23.4.1 shows the die floor plan using a quad-plane architecture. The chip is divided into four 2Gb arrays with each array consisting of 512 blocks and each block consisting of 128 pages. The block size is 512K bytes and the page size is 4K bytes. The control, I/O, and the supply pads are located on the right side of the chip. A few supply pads are also located on the left side of the chip but embedded within the peripheral circuits. This mainly one-sided pad arrangement is selected to reduce the die size while maintaining good power distribution for the high-voltage pumps and logic in the peripheral circuit section. With this architecture, a cell area efficiency of 65% is achieved. This is comparable with other highdensity NAND Flash designs using a conventional two-plane architecture. We achieve 100MB/s program throughput by extending the page size to 16KB in quad-plane mode and by using a 160µs programming time. The use of the 64-cell string reduces the bitline length thereby reducing the bitline RC. To compensate for the increase in string resistance in going from the 32-cell string to the 64-cell string, we develop a wordline voltage modulation scheme, shown in Fig. 23.4.2. During the read cycle, the wordline voltage of the unselected cells is modulated by the location of the selected cell on the string. The wordlines are divided into 4 groups: A for 0 to 15, B for 16 to 31, C for 32 to 47, and D for 48 to 63. The group corresponding to the selected cell determines the voltage level (Vread) of the unselected wordlines. Thus, a higher wordline voltage level is used if accessing a cell near the top of the string (bitline) to compensate for the string resistance. Figure 23.4.3 shows how the chip transitions from the asynchronous to synchronous interface and vice versa. The chip is powered up in the standard asynchronous NAND interface mode, and is switchable between the synchronous DDR and the asynchronous interfaces at anytime after power up using the set feature command (EFh). During the interface change time (t ITC ), the chip switches to the desired interface.
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