A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s

Abstract

In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm 2 .The chip is divided into four 8Gb arrays. Each array consists of 684 blocks and each block consists of 384 pages. The page size is 4KB that can be extended to 16KB in quad-plane operation. The chips main features are summarized in Fig. 24.7.1.A technique called source-bias read/verify, consisting in raising the source voltage during read, is been implemented to widen the V T allocation window. A new sensing technique is adopted to ensure that the BL-to-source-voltage difference remains constant as the source voltage is raised during read. The LMU technique, consisting in programming lower (L), middle (M) and upper (U) pages in consecutive order, as shown in Fig. 24.7.2, is adopted to improve the precision of distribution placement by mitigating the floating-gate interference (FG-FG) [5]. The first pulse ramp technique [6][7], consisting in shaping the first program and erase pulse with an initial voltage ramp, is implemented to better preserve oxide integrity and, therefore, data retention. The final distributions achieved with all the above-mentioned techniques are shown in Fig 24.7.3.The chip supports asynchronous data I/O at 20ns cycle time and synchronous DDR access at an I/O rate of 6ns/byte. This read performance is achieved by using the data path architecture shown in Fig. 24.7.4. The architecture is based on the following key design points: four bytes simultaneous sensing in a plane, three stages pipeline and byte mux at I/O pads level. The first stage pipe is to account for RE# and column-address counter propagation; the second stage pipe is to account for address decoder, cache selection and second sensing (SSA) propagation; the third stage pipe is to account for plane mux and data propagation. Multi-plane operations are supported up to a maximum of four planes.The analog system features 10-bit resolution. A digital thermometer is developed for on-chip temperature compensation of array operation. Most of the 3b/c related features are implemented by enhancing the controllability of the analog block by the chip controller via dedicated control registers and by performing all accurate analog operations in precision low-voltage low-noise analog-signal-level (ASL) circuitry built around a 10-bit resistor ladder, as shown in Fig. 24.7.5. In this ap...

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