A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface

Abstract

NAND flash has been steadily growing in popularity among different applications such as SSD, hybrid HDD, and game consoles; and new applications are emerging that require higher read/write performance. A 3.3V 8Gb NAND Flash memory with a synchronous double-data-rate (DDR) interface is designed and fabricated using 3M 50nm technology to meet the requirements of these markets. We achieve a NAND Flash program throughput of 100MB/s with quad-plane operation, which is 5× previously reported [1,2]. I/O read/write throughput of 200MB/s is achieved using a newly developed DDR interface [3] and data path [4]. The chip features a dual interface, supporting both the newly developed synchronous DDR interface as well as the standard, asynchronous NAND Flash interface. A 64-cell string [5] is adopted to reduce the effective cell size, including the select transistors, to 0.011µm 2 and reduce the die size to 169.5mm 2 . Figure 23.4.1 shows the die floor plan using a quad-plane architecture. The chip is divided into four 2Gb arrays with each array consisting of 512 blocks and each block consisting of 128 pages. The block size is 512K bytes and the page size is 4K bytes. The control, I/O, and the supply pads are located on the right side of the chip. A few supply pads are also located on the left side of the chip but embedded within the peripheral circuits. This mainly one-sided pad arrangement is selected to reduce the die size while maintaining good power distribution for the high-voltage pumps and logic in the peripheral circuit section. With this architecture, a cell area efficiency of 65% is achieved. This is comparable with other highdensity NAND Flash designs using a conventional two-plane architecture. We achieve 100MB/s program throughput by extending the page size to 16KB in quad-plane mode and by using a 160µs programming time. The use of the 64-cell string reduces the bitline length thereby reducing the bitline RC. To compensate for the increase in string resistance in going from the 32-cell string to the 64-cell string, we develop a wordline voltage modulation scheme, shown in Fig. 23.4.2. During the read cycle, the wordline voltage of the unselected cells is modulated by the location of the selected cell on the string. The wordlines are divided into 4 groups: A for 0 to 15, B for 16 to 31, C for 32 to 47, and D for 48 to 63. The group corresponding to the selected cell determines the voltage level (Vread) of the unselected wordlines. Thus, a higher wordline voltage level is used if accessing a cell near the top of the string (bitline) to compensate for the string resistance. Figure 23.4.3 shows how the chip transitions from the asynchronous to synchronous interface and vice versa. The chip is powered up in the standard asynchronous NAND interface mode, and is switchable between the synchronous DDR and the asynchronous interfaces at anytime after power up using the set feature command (EFh). During the interface change time (t ITC ), the chip switches to the desired interface.

Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

“…1176 Larger number of array cells leads to a reduced sensing current and increased access times. 1177 For these reasons, alternative materials and storage concepts have been actively investigated, including implementation of graphene in non-volatile memories 1140,[1178][1179][1180][1181][1182] see Fig. 60.…”

Non-volatile Random Access Memory and NAND Flash Memory Integrated Solid-State Drives with Adaptive Codeword Error Correcting Code for 3.6 Times Acceptable Raw Bit Error Rate Enhancement and 97% Power Reduction

“…For the NAND interface, eight I/O pins 40 MHz double data rate (DDR)/toggle-mode interface is assumed. 4,5) At the 10 Gbps write, the proposed SSD decreases the power consumption by 97% which is discussed in detail in the next section. In the proposed ECC, errors of both NV-RAM and the NAND flash memory are corrected without circuit area overhead by sharing the same ECC circuits.…”

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

“…This is not only due to device size and V DD scaling while keeping the same threshold voltage (V TH ), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1][2] to achieve smaller area-per-bit; 2) lower-V DD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller I CELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (C BL ) mismatches and 2) V TH variation.…”

“…Many small-I CELL NVMs employ voltage-mode SA (VSA) [2] with a long BL developing time to tolerate SA offset, at the cost of a reduced read speed. Current-mode SA (CSA) achieves faster read speeds than VSA [1].…”