We present SysPy (System Python) a tool which exploits the strengths of the popular Python scripting language to boost design productivity of embedded System on Chips for FPGAs. SysPy acts as a "glue" software between mature HDLs, ready-to-use VHDL components and programmable processor soft IP cores. SysPy can be used to: (i) automatically translate hardware components described in Python into synthesizable VHDL, (ii) capture top-level structural descriptions of processor-centric SoCs in Python, (iii) implement all the steps necessary to compile the user's C code for an instruction set processor core and generate processor specific Tcl scripts that import to the design project all the necessary HDL files of the processor's description and instantiate/connect the core to other blocks in a synthesizable top-level Python description. Moreover, we have developed a Hardware Abstraction Layer (HAL) in Python which allows user applications running in a host PC to utilize effortlessly the SoC's resources in the FPGA. SysPy's design capabilities, when complemented with the developed HAL software API, provide all the necessary tools for hw/sw partitioning and iterative design for efficient SoC's performance tuning. We demonstrate how SysPy's design flow and functionalities can be used by building a processor-centric embedded SoC for computational systems biology. The designed SoC, implemented using a Xilinx Virtex-5 FPGA, combines the flexibility of a programmable soft processor core (Leon3) with the high performance of an application specific core to simulate flexibly and efficiently the stochastic behavior of large size biomolecular reaction networks. Such networks are essential for studying the dynamics of complex biological systems consisting of multiple interacting pathways.
Although software engineers have high performance algorithms that could be implemented power-efficiently as embedded Systems on Chip (SoC) with modem FPGAs, there is still no easy path for them to a hardware realization, mainly due to the lack of appropriate de sign tools. We present an overview of a tool we have developed to boost the productivity of processor-centric SoC designs for FP GAs. Our tool called SysPy (System Python) exploits the strengths of the popular Python scripting language and acts as a "glue soft ware" between mature HDLs, ready-to-use VHDL components and programmable processor soft IP cores. SysPy can be used to: (i) describe hardware components in Python that the tool will automat ically translate to correct high quality VHDL, (ii) build top-level structural descriptions of SoCs based on components that are de fined in Python, VHDL or pre-synthesized netlist files, (iii) imple ment without any user effort all the steps needed to take the user's C code for a programmable processor soft IP core and automatically produce a synthesizable VHDL description for the targeted Xilinx FPGA device. The top-level SoC description is in Python, facili tating Hw/Sw re-partitioning and efficient iterative design for SoC performance tuning.
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