High Throughput Systolic SOM IP Core for Fpgas

ACM Trans. Embed. Comput. Syst.

2013

We designed a variety of k-nearest-neighbor parallel architectures for FPGAs in the form of parameterizable soft IP cores. We show that they can be used to solve large classification problems with thousands of training vectors, or thousands of vector dimensions using a single FPGA, and achieve very high throughput. They can be used to flexibly synthesize architectures that also cover: 1NN classification (vector quantization), multishot queries (with different k), LOOCV cross-validation, and compare favorably to GPU implementations. To the best of our knowledge this is the first attempt to design flexible IP cores for the popular kNN classifier. ACM Reference Format:Stamoulias, I. and Manolakos, E. S. 2013. Parallel architectures for the kNN classifier -Design of soft IP cores and FPGA implementations.

Section: Architecture Designmentioning

confidence: 99%

Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

ACM Trans. Embed. Comput. Syst.

2013

“…Specifically, if a stream of m query vectors is presented to the system for classification, element-by-element the one after the other, it takes overall T m cycles (1) to produce the results and the performance is P m operations/sec given by (2). As the number of input vectors that are pipelined increases, the performance P m becomes in the limit P b (3).…”

Section: Introductionmentioning

confidence: 99%

“…Afterwards, when a query vector Y is presented to the system for classification, its distance to each one of the reference vectors is calculated and the "k" smallest distances are found. The Euclidean distance metric is usually employed, but for a hardware implementation, as with other classifier designs, the Manhattan distance is often preferred, since it is simpler to realize [2]. Finally, the class label of the query vector is determined as the label that is encountered most times among its k nearest neighbor labels.…”

Section: Introductionmentioning

confidence: 99%

Flexible IP cores for the k-NN classification problem and their FPGA implementation

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

2010

The k-nearest neighbor (k-NN) is a popular nonparametric benchmark classification algorithm to which new classifiers are usually compared. It is used in numerous applications, some of which may involve thousands of data vectors in a possibly very high dimensional feature space. For real-time classification a hardware implementation of the algorithm can deliver high performance gains by exploiting parallel processing and block pipelining. We present two different linear array architectures that have been described as soft parameterized IP cores in VHDL. The IP cores are used to synthesize and evaluate a variety of array architectures for a different k-NN problem instances and Xilinx FPGAs. It is shown that we can solve efficiently, using a medium size FPGA device, very large size classification problems, with thousands of reference data vectors or vector dimensions, while achieving very high throughput. To the best of our knowledge, this is the first effort to design flexible IP cores for the FPGA implementation of the widely used k-NN classifier.

“…When an unseen test vector Y is presented for classification, its distance to each one of the stored training vectors is calculated and the "k" smallest distances are retained. The Euclidean distance metric is usually employed, however for a hardware implementation, as with other classified designs, the Manhattan distance is often preferred, since it is simpler to realize in hardware [7]. Finally, the class label of the test vector is determined as the one that is encountered most times among its k nearest neighbor labels.…”

Section: Introductionmentioning

confidence: 99%

IP-cores design for the kNN classifier

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

2010

We present the systematic design of two linear array IP cores for the k-nearest neighbor (k-NN) benchmark classifier. The need for real-time classification of data vectors with possibly thousands of features (dimensions) motivates the implementation of this widely used algorithm in hardware in order to achieve very high performance by exploiting block pipelining and parallel processing. The two linear array architectures that we designed have been described as soft IP cores in fully parameterizable VHDL that can be used to synthesize effortlessly different k-NN parallel architectures for any desirable combination of the problem size parameters. They have been evaluated for a large variety of parameter combinations and Xilinx FPGAs. It is shown that they can be used to solve efficiently very large size k-NN classification problems, even with thousands of training vectors or vector dimensions, using a single, moderate size FPGA device. Furthermore the FPGA implementations exceed by a factor of two the performance of optimized NVIDIA CUDA API software implementations for the powerful GeForce 8800GTX GPU.