Python to accelerate embedded SoC design

Abstract

We present SysPy (System Python) a tool which exploits the strengths of the popular Python scripting language to boost design productivity of embedded System on Chips for FPGAs. SysPy acts as a "glue" software between mature HDLs, ready-to-use VHDL components and programmable processor soft IP cores. SysPy can be used to: (i) automatically translate hardware components described in Python into synthesizable VHDL, (ii) capture top-level structural descriptions of processor-centric SoCs in Python, (iii) implement all the steps necessary to compile the user's C code for an instruction set processor core and generate processor specific Tcl scripts that import to the design project all the necessary HDL files of the processor's description and instantiate/connect the core to other blocks in a synthesizable top-level Python description. Moreover, we have developed a Hardware Abstraction Layer (HAL) in Python which allows user applications running in a host PC to utilize effortlessly the SoC's resources in the FPGA. SysPy's design capabilities, when complemented with the developed HAL software API, provide all the necessary tools for hw/sw partitioning and iterative design for efficient SoC's performance tuning. We demonstrate how SysPy's design flow and functionalities can be used by building a processor-centric embedded SoC for computational systems biology. The designed SoC, implemented using a Xilinx Virtex-5 FPGA, combines the flexibility of a programmable soft processor core (Leon3) with the high performance of an application specific core to simulate flexibly and efficiently the stochastic behavior of large size biomolecular reaction networks. Such networks are essential for studying the dynamics of complex biological systems consisting of multiple interacting pathways.

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

“…SysPy [10] (released in 2012) is one of the high-level co-design approaches. It provides a platform that allows the synthesis of hardware behaviors, and design SoC centric:…”

“…SysPy provides a communication interface between the SoCs, and the hot computer [10], through a HAL hardware abstraction layer. This gives access to the FPGA communication channels (GPIO, Ethernet), and the RAM.…”

Enabling transparent hardware acceleration on Zynq SoC for scientific computing

“…It is also interesting to notice that there are several projects that rely on Python to design hardware [9][10][11], although they utilize the Python syntax for low-level hardware description, in a way that is functionally equivalent to using classical Hardware Description Languages (HDLs). However, this approach is transversal to the approach proposed in this paper, as we rely on overlays, i.e.…”

Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks

“…Find the reaction Rμ that has the smallest putative time τ =min{τj}. 4. Determine the new time and system state after firing reaction Rμ:…”

“…However the design of such aggressively pipelined Systems on Chip (SoC) is still a complex process where the designer should strike a good balance between the complexity of the class of bio-models supported by the SoC and the size of the FPGA device used, in terms of on-chip resources (LUTs, RAMs and DSPs). Examples of FPGA solutions are those in [4], [5]. Likewise, GPU based solutions, such as [6] and [7], exploit the massively parallel compute power of GPUs that are nowadays readily available on the average scientist's PC.…”