T h i s p a p e r d e s c r i b e s t h e n e w wrlte/erase operation methods in order to improve the read disturb characteristics for Flash EEPROM cells which are written by c h a n n e l hot electron injection and erased by F-N tunneling emission from the floating gate to the substrate. The new o p e r a t i o n . m e t h o d s is either applying a reverse polarity pulse after each erase pulse o r applying a series o f shorter erase pulses instead o f a l o n g single erase pulse. It is confirmed that by using the above operation methods, the leakage current can be suppressed, and then the read disturb life time after 10" cycles W/E operation is more than 10 times longer i n c o m p a r i s o n w i t h t h e c o n v e n t l o n a l method.
Takasaki Works, Hitachi Ltd. 111, Nishiyokote Takasaki-shi, Gunma, 370-11 Japan INTRODUCTION S i n c e Bi-CMOS technology employs highd r i v a b i l i t y g a t e c i r c u i t s and h i g h -s e n s i t i v i t y Sense c i r c u i t s , h i g h e r speed memory c i r c u i t s than t h o s e through CMOS p r o c e s s technology can b e a c h i e v e d . This paper d e s c r i b e s 64K TTL SRAM d e s i g n u s i n g 1 . 3 u m Hi-BiCMOS technology. A 16Kw x 4b o r 64Kw x Ib RAM i s c o n f i g u r a b l e by changing t h e w i r i n g l a y e r c o n f i g u r a t i o n . I n t h i s RAM, t h e c u r r e n t source c i r c u i t i s s t a b i l i z e d a g a i n s t power-supply v o l t a g e Vcc and t e m p e r a t u r e so t h a t i n c r e a s e i n a c c e s s time a s w e l l a s i n power consumption under t h e w o r s t c o n d i t i o n s a r e minimized. The a d d r e s s a c c e s s time of t h e RAM i s 8.0 ns and t h e a c t i v e c u r r e n t i s 45 mA under t h e c o n d i t i o n s of Vcc=5.0 V , Ta=25"C, and 50 M H r . DEVICE STRUCTURE The 1 . 3 um Hi-BiCMOS technology used f o r t h i s RAM i s summarized i n Table 1. The minimum g a t e l e n g t h i s 1 . 2 um and t h e g a t e o x i d e t h i c k n e s s i s 20 nm. The minimum emitter s i z e of t h e b i p o l a r t r a n s i s t o r i s I x 3 um and t h e c u to f f frequency i s 6 GHa. The b i p o l a r t r a n s i s t o r ' s c o l l e c t o r and t h e PMOS t r a n s i s t o r ' s N-well a r e a a r e formed by an N-type e p i t a x i a l l a y e r on P-type s u b s t r a t e and an N' b u r i e d l a y e r . c e , and g a t e c i rc u i t s a r e a r r a n g e d f o r t h e s h o r t e s t s i g n a l l i n e s . CIRCUITS A b i p o l a r ECL c i r c u i t i s used as a s e n s e a m p l i f i e r t o speed up t h e memory d a t a r e a d . However, t h i s c i r c u i t consumes c o m p a r a t i v e l y much power w i t h r e s p e c t t o t h e RAM'S t o t a l power consumption. I n t h i s RAM, access time and power consumption under t h e w o r s t c o n d i t i o n s are improved by s t a b i l i z i n g t h e c u r r e n t source of t h e sense c i r c u i t a g a i n s t Vcc and temperature. The c u r r e n t g e n e r a t o r and sense a m p l i f i e r c i r c u i t a r e shown i n F i g . 2 . The c u r r e n t g e n e r a t o r c i r c u i t i s composed of b i p o l a r t r a n s i s t o r s and r e s i s t o r s , which compensates f o r t h e dependency of t h e curr e n t value on Vcc and t e m p e r a t u r e . C u r r e n t o u tput from t h e c u r r e n t g e n e r a t o r circuit i s c o n v e r t e d t o NMOS t r a n s i s t o r ' s g a t e v o l t a g e by t h e CMOS c u r r e n t m i r r o r c i y c u i t , and t h e v o l t a g e i s s u p p l i e d t o t h e NMOS c u r r e n t source of t h e sense c i r c u i t . S i n c e t h e c u r r e n t value of t h e NMOS c u r r e n t source i s determined by t h e r a t i o between t h e NMOS g a t e w i d t h Wnl of t h e c u r r e n t m i r r o r c i r c u i t and ...
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