Timepix4 is a 24.7 × 30.0 mm2 hybrid pixel detector readout ASIC which has been designed to permit detector tiling on 4 sides. It consists of 448 × 512 pixels which can be bump bonded to a sensor with square pixels at a pitch of 55 µm. Like its predecessor, Timepix3, it can operate in data driven mode sending out information (Time of Arrival, ToA and Time over Threshold, ToT) only when a pixel has a hit above a pre-defined and programmable threshold. In this mode hits can be tagged to a time bin of <200 ps and Timepix4 can record hits correctly at incoming rates of ∼3.6 MHz/mm2/s. In photon counting (or frame-based) mode it can count incoming hits at rates of up to 5 GHz/mm2/s. In both modes data is output via between 2 and 16 serializers each running at a programmable data bandwidth of between 40 Mbps and 10 Gbps. The specifications, architecture and circuit implementation are described along with first electrical measurements and measurements with radioactive sources. In photon counting mode X-ray images have been taken at a threshold of 650 e− (with <10 masked pixels). In data driven mode images were taken of ToA/ToT data using a 90Sr source at a threshold of 800 e− (with ∼120 masked pixels).
Power consumption is always a concern in the design of readout chips for hybrid pixel detectors. The Timepix3 chip is capable of dealing with up to 80 Mhits/cm 2 /sec and tagging each hit within a time bin of 1.56 ns. At full speed the Timepix3 chip will consume 1.3 W. We consider how to reduce power consumption if hit rate and/or time stamp precision is not important. The analog power can be reduced by more than an order of magnitude with little impact on noise by reducing the bias current of the input transistor and increasing the return to zero time of the preamplifier. Digital power consumption might be ∼ 6× lower by reducing the clock frequency to 1 MHz from the nominal 40 MHz. Simulations and measurements are presented. In very low power mode Timepix3 could consume only ∼150 mW on 2 cm 2 .The new Timepix4 chip aims at time tagging within a bin of 200 psec. Propagation of a 5 GHz clock around the pixel matrix would be impractical. We present a novel architecture implementing a very low jitter clock to the full pixel matrix. A digital Delay Locked Loop is designed in which the delay chain is distributed along the two columns of each super-pixel with the phase comparator and control located at the base of the double column. The control system locks all super-pixels to the low jitter (<100 ps) global 40 MHz clock. Simulations show that this can be achieved with a power consumption of only 25 mW/cm 2 while preserving high rate capability.
A fully differential self-biased inverter-based folded cascode amplifier which uses the feedforward-regulated cascode principle is presented. A detailed small-signal analysis covering both the differential-mode and the common-mode paths of the amplifier is provided. Based on these theoretical results a design is given and transistor level simulations validate the theoretical study and also demonstrate the efficiency and usefulness of the proposed amplifier.
high conversion rates are required. With advances of the CMOS technology, the conversion rates of CMOS ADCs are now well beyond the gigasamples per second (GS/s) range, but only moderate resolutions are required [4]. These ADCs need to be tested after fabrication and, if possible, during field operation. The test costs are a very significant fraction of their production cost [5]. This is mainly due to lengthy use of very expensive automated test equipment (ATE) to apply specific test stimuli to the devices under test (DUT), and to collect and analyse their responses. With high conversion rates it is difficult to interface the ADCs to the test instruments due: extra parasitics, line trace mismatches, interferences within the printed circuit board (PCB), and the instrument test probes. This becomes even more challenging in the case of systems-on-a-chip, system-in-a-package, and three-dimensional (3D) chips, where the accessibility of the ADCs for testing purposes is restricted [6]. In this paper we discuss the use of built-in self-test (BIST) techniques for testing high speed ADCs and we present a specific solution, in which the analog input signal and the clock are generated internally. BIST for High Speed ADCs Using advanced CMOS technologies, the cost per transistor decreases and integrated solutions become competitive. Thus, more specific functionalities can be fully integrated on-chip. Moreover, the reliability of the manufacturing process maintains high, allowing reliable function to be implemented on-chip as well. The implementation of test-related functions directly on-chip during the IC design phase, which is called design for testability, evolved firstly for purely digital ICs and then migrated to mixed-signal devices. Using a BIST approach contributes to additional area, increases design time and effort, and may degrade the performance of the DUT due to intrusive test structures. Table 1 summarizes the pros and cons of a BIST solution. * Do not deal with the clock signal generation. † Area of the read-only memory not included. ‡ SFDR measured at 1 MHz frequency. § Ignoring PLLs reference spurs. * * Jitter rms integrated above 1 MHz and estimated from simulation.
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