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In this paper we introduce, a state-of-the-art SiGe BiCMOS power amplifier technology that features two NPNs with 40 GHz / 6.0 V & 27 GHz / 8.5 V (fT -BVceo) respectively, a novel low inductance metal ground through-silicon-via (TSV), integrated on a low-cost 0.35 ,um lithography node with 3.3 V / 5.0 V dualgate CMOS technology and high-quality passives on a 50 Q.cm substrate. INTRODUCTIONToday for RF radio applications, the system is partitioned to minimize the overall cost, size, and power. Competing approaches with system-on-a-chip and system-in-a-package effectively address this system partitioning. Based on these approaches, the RF transceiver and front-end-modules (FEM) integration is still a battleground for multiple technologies. Of particular interest is the power amplifier (PA) integration trend. Compared to the transceiver, the FEM elements, such as, PA and switch need to support very harsh environment for power and linearity. Stringent system specifications requirements related to output power, linearity, efficiency etc. force system designers to partition the FEM as a separate packaged module. In effect, this allows the use of best possible technology for the lowest cost module [1]. This situation is expected to get worse in future wireless communication systems where the FEMs need to integrate multi-mode and multi-band PAs with better form-factor and cost. Silicon technology remains as an excellent candidate for providing such an integration path. SiGe BiCMOS has made substantial in-road into PA market segment with the explosion of WLAN applications at 2.4 GHz. A 0.5um SiGe BiCMOS technology [2] optimized for power amplifier design has provided a stepping stone for this application. SiGe BiCMOS integration allows several benefits compared to GaAs HBTs, such as, integrated biasing and regulator to manage battery voltage, temperature compensated

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PURPOSE-TI --TIThis paper will demonstrate the effect of a new low-cost oxide filled trench isolation structure, and implanted sub-collectors on the latchup robusmess. With scaling and focus on low-cost wireless technology, new technologies are being developed utilizing a shallower oxide-filled trench structure and low-doped implanted subcollectors, In this paper, the first latchup measurements and corresponding new discoveries will be shown utilizing this new isolation structure and its integration with implanted sub-collectors. This paper will compare latchup measurements with the base CMOS technology (e.g. standard dual well p-substrate base technology) to quantify the net improvement. The results will be shown with trench isolation only, sub-collector only, and the combined effect of the trench isolation and sub-collector [Keywords.' Latchup, Trench Isolation (TI), Implanted Sub-collector, Silicon Germanium (SiGe)] CMOS latchup has been a concern in the semiconductor industry from 1970's to the present day . CMOS latchup solutions have included p+ substrates [ 12-16,221, retrograde n-wells [22-241, shallow trench isolation [24], heavily doped buried layer [25-30,32 1, and buried grids [32]. But, BiCMOS SiGe HBT technology is placed in low doped p-substrate to provide noise isolation between digital, analog and RF circuits [45,46]; this low doped substrate unfortunately increases the latchup sensitivity, The scaling trend in Rf CMOS, and RF BiCMOS SiGe technology is to lower the substrate doping Concentration for lower substrate capacitance, lower noise, and improved "Q" for RF passives [33]. To improve the Iatchup robustness of BiCMOS technology, latchup solutions have been shown using 5.5 pm polysilicon-filled deep trench @T) isolation [34-40], heavily doped epitaxial-formed sub-collectors [37-40,431, as well as p+ buried layers [30]. Polysilicon-filled deep trench (DT) isolation and heavily doped epitaxy-formed subcollectors provide excellent latchup improvement [34-401. In this paper, a less expensive process is to form a shallower oxide-filled trench isolation (TI) stmcture. Additionally, a shallower, low-dose sub-collector can also be placed in the n-well region to improve the latchup robustness. Figure 1 shows an example of CMOS technology with shallow trench isolation (STI). In a mainstream CMOS technology, the substrate is a p-doping concentration with a high resistivity. The nwell region is an implanted retrograde well with sheet resistance in the range of 300 to 800 ir /sq. The p-well region is also formed using implantation, and the doping concentration is significantly above the base p-substrate wafer. The p-well and n-well implantation doses are defined so that the junction is formed under the shallow trench isolation (STI) bottom region. The design point for the p-well and nwell dose is a function of the back-bias requirements on the MOSFET structure, as well as the ability to place the p-well-to-nwell metallurgical junction requirements. 0-7803-8803-8/05/$20.00 02005 IEEE I N-Well I P-Substrat...

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