Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications

Joseph, A.J.; Gillis, John; Doherty, Mark; Lindgren, Peter; Previti-Kelly, R.; Malladi, R.M.; Wang, P.-C.; Erturk, M.; Ding, Hanyi; Gebreselasie, E.; McPartlin, Mike; Dunn, James

doi:10.1147/jrd.2008.5388563

Cited by 35 publications

(20 citation statements)

References 14 publications

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“…polymers, followed by appropriate thermal processing and removal of excess material from the surface. Extensive work has been done in the development of each of these processes, and the characterization of the resulting TSV's at a variety of dimensions and pitches [24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43].…”

Section: Tsv Processesmentioning

confidence: 99%

“…In a true via-first process, vias are etched at the very beginning, whereas in the instance of via etching after most silicon fabrication is complete, vias are etched last. A comparison of these process flows is shown in Figure 7 [24], whereas a via-middle process flow is shown in Figure 8 [25]. The TSV diameter, depth and pitch are also key factors in the choice of etch method.…”

Section: Tsv Processesmentioning

confidence: 99%

“…Constructing a Figure 9 Schematic of the Bosch process [43]. 25 µm deep TSV with an aspect ratio of ∼5:1 in the middle of the back end process [26] may require a different technique compared to a process that requires very deep TSVs, in the 100 µm range, with aspect ratios approaching 50:1, at the start of silicon processing [25]. For etching through silicon, a commonly employed technique is the Bosch process which has alternating cycles of passivation (C4F8) to prevent lateral etching, followed by Si etch (SF6) [43,44].…”

Section: Tsv Processesmentioning

confidence: 99%

“…Aspect ratios of better than 40:1 are achievable by this method. Several researchers have used the Bosch method for their TSV evaluations [25,27,28,34,42]. Others have investigated non-Bosch TSV etch processes, such as a magnetically-enhanced capacitively-coupled plasma etch method, to achieve aspect ratios approaching 30:1 [30] or an enhanced etch process to achieve deep vias with minimal sidewall roughness, i.e.…”

Section: Tsv Processesmentioning

confidence: 99%

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3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Section: Tsv Processesmentioning

confidence: 99%

Section: Tsv Processesmentioning

confidence: 99%

Section: Tsv Processesmentioning

confidence: 99%

Section: Tsv Processesmentioning

confidence: 99%

See 2 more Smart Citations

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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show abstract

“…We assume that TSV integration scheme is via-first, and the TSV aspect ratio is 30:1. High TSV aspect ratios of more than 30:1 were demonstrated in [1]. For thick dies, a high TSV aspect ratio is needed to handle many die-to-die interconnects.…”

Section: Signal Interconnectmentioning

confidence: 99%

Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs

Lee

Goel

Lim

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-vias (TTSVs) and micro-fluidic channel (MFC) based liquid cooling. In case of power delivery, a highly complex power distribution network is required to deliver currents reliably to all parts of the 3D stacked IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. This is because the signal, power, and thermal interconnects are all competing for routing space. In this paper, we present a co-optimization methodology for the signal, power, and thermal interconnects for 3D stacked ICs based on design of experiments (DOE) and response surface method (RSM). The goal is to improve performance, thermal, noise, and congestion metrics with our holistic approach. We also provide in-depth comparison between T-TSV and MFC based cooling method and discuss how to employ DOE and RSM to best co-optimize the multi-functional interconnects simultaneously.

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Electrical Design for 5G Hardware—Digital Focus

Hwang¹,

Horng²

2018

3D IC and RF SiPs

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Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications

Cited by 35 publications

References 14 publications

3D integration review

3D integration review

Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs

Electrical Design for 5G Hardware—Digital Focus

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