Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs

Abstract

Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-vias (TTSVs) and micro-fluidic channel (MFC) based liquid cooling. In case of power delivery, a highly complex power distribution network is required to deliver currents reliably to all parts of the 3D stacked IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. This is because the signal, power, and thermal interconnects are all competing for routing space. In this paper, we present a co-optimization methodology for the signal, power, and thermal interconnects for 3D stacked ICs based on design of experiments (DOE) and response surface method (RSM). The goal is to improve performance, thermal, noise, and congestion metrics with our holistic approach. We also provide in-depth comparison between T-TSV and MFC based cooling method and discuss how to employ DOE and RSM to best co-optimize the multi-functional interconnects simultaneously.

Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures

“…Prior work on thermal management for 3-D MPSoCs mainly addresses design-time optimization, such as thermally aware floorplanning [16], integrating thermal via planning in the 3-D floorplanning process [22], and joint optimization that targets temperature, power interconnect, and signal wires [20]. A tradeoff study in recent work compares thermal behavior and interconnect congestion for two 3-D MPSoC cooling technologies: inter-tier liquid cooling and thermal throughsilicon-vias (TSVs) [20].…”

“…A tradeoff study in recent work compares thermal behavior and interconnect congestion for two 3-D MPSoC cooling technologies: inter-tier liquid cooling and thermal throughsilicon-vias (TSVs) [20]. This paper shows that inter-tier liquid cooling has superior cooling abilities, but induces limitations for TSVs and increases cost with respect to using thermal TSVs only.…”

Thermal modeling and analysis of 3D multi-processor chips

“…During the last years, many fabrication-based solutions for the thermal management in 3D integrated circuits have been proposed [34]. Thermal through silicon vias (TTSVs) have a prominent place among these solutions.…”

Assembling 2D blocks into 3D chips

“…Some studies explicitly consider thermal TSV insertion but not signal TSVs [20,22,23,29]. Other studies incorporate signal and power TSVs in their flow, but sometimes ignore footprints of signal TSVs [18,19].…”