Abstract-In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the nonprogrammed eFuse is reduced from 728 µA to 61 µA when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 kΩ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).
Abstract-In this paper, we design a 256 kbits EEPROM for a MCU (Microcontroller unit) with the wide voltage range of 1.8 V to 5.5 V. The memory space of the EEPROM is separated into a program and data region. An option memory region is added for storing user IDs, serial numbers and so forth. By making HPWs (High-voltage P-wells) of EEPROM cell arrays with the same bias voltages in accordance with the operation modes shared in a double word unit, we can reduce the HPW-to-HPW space by a half and hence the area of the EEPROM cell arrays by 9.1 percent. Also, we propose a page buffer circuit reducing a test time, and a write-verify-read mode securing a reliability of the EEPROM. Furthermore, we propose a DC-DC converter that can be applied to a MCU with the wide voltage range. Finally, we come up with a method of obtaining the oscillation period of a charge pump. The layout size of the designed 256 kbits EEPROM IP with MagnaChip's 0.18 µm EEPROM process is 1581.55 µm × 792.00 µm.
A 1 kbit antifuse one time programmable (OTP) memory IP, which is one of the non-volatile memory IPs, was designed and used for power management integrated circuits (ICs). A conventional antifuse OTP cell using a single positive program voltage (V PP ) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time, securing the reliability of medium voltage (V M ) devices that are thick gate transistors. A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop. For the newly proposed cell, a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse. The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek's 0.18 µm Bipolar-CMOS-DMOS (BCD) process is 567.9 μm×205.135 µm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.
We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. 256-KBit EEPROM IP is designed using MagnaChip's 0.18μm EEPROM process. The layout size of the designed 256-KBit EEPROM IP is 1765.05μm × 691.71μm.
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