A fully functional Si photonics and 65-nm CMOS heterogeneous 3D integration is demonstrated for the first time in a 300mm production environment. Direct oxide wafer bonding was developed to eliminate voids between SOI photonics and bulk Si CMOS wafers. A via-last, Cu through-oxide via (TOV) 3D integration was developed for low capacitance electrical connections with no impact on CMOS performance. 3D yield approaching 100% was demonstrated on >20,000 via chains.
A fully functional Si photonics and 65-nm complementary metal-oxide semiconductor (CMOS) heterogeneous three-dimensional (3-D) integration is demonstrated for the first time in a 300-mm production environment. Direct oxide wafer bonding was developed to eliminate voids between silicon on insulator photonics and bulk Si CMOS wafers. A via-last, Cu through-oxide via 3-D integration was developed for low capacitance electrical connections with no impact on the CMOS performance. The 3-D yield approaching 100% was demonstrated on >20,000 via chains.
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