Metal transparent conductive films (TCFs) have received increasing attention in various flexible electronics. However, there are two crucial issues that need to be addressed: (1) strong adhesion between metal TCFs and the flexible substrates and (2) high conductivity with short treatment time and low process temperature, simultaneous with high transparency. In this paper, a site-selective electroless plating combination with poly(dopamine) modification is demonstrated to fabricate a new high performance transparent conductor composed of a periodic two-dimensional silver network on a heat sensitive flexible substrate at room temperature. The TCF reveals an extremely high ratio of DC to optical conductivity (σ(DC)/σ(Op)) value in the range of 350-1000 for various fabricated silver grid films. It also exhibits particularly strong adhesion, which can resist ultrasonic treatment in water or organic solvent for several hours. Its reliability (stable for at least 1440 h during 85 °C/85% RH aging) meets the essential requirements for microelectronic applications. Using this method, we obtain silver grid film on a flexible polyethylene terephthalate substrate with optical transmittance of 91% and sheet resistance of 8 Ohm sq(-1), which is comparable to or better than the commercially available indium tin oxide.

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FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Wafer level packaging (WLP) is regarded as one of the most potential single chip packages for its compatibility with wafer fabrication process. As the pitch size of the package becomes lower, the reliability of fme pitch WLP devices is greatly challenged. Finer pitch may result in weaker solder joints, which leads to reliability problems such as fatigue failure, creep deformation and so on. Much work has been done to investigate the reliability of wafer level package above 500 f!m pitch under different conditions such as temperature cycling, thermal shock and drop test, etc. Nevertheless, there are few reports about the reliability of WLP with pitch size less than 500 f!m. In this study, WLP with a size of 5x5 mm 2 and a pitch of 400 f!m were fabricated. Each chip has 144 lead-free SAC105 solder balls in an array of 12x12. The chips are retlowed on Nil Au pads on boards. The chips were experienced a set of reliability tests including temperature cycling, thermal shock and drop test according to JEDEC standards. Furthermore, failure analysis is carried out to study the failure mechanism. Failures are found mostly inside of the solder ball after TC and TS tests, while the drop tests cause more damage to the solder-board and solder-chip interface.