FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.
The dropping test of WLCSP with RDL on boardlevel was investigated by numerical method in this study. The asymmetric pattern of WLCSP devices mounted on the PCB board was considered. Using the finite element analysis, the stress and energy in the WLCSP with RDL was predicted under the dropping test conditions. The critical locations of WLCSP device on the PCB in the dropping test were identified by effective models, which simplified the detail structures, e.g. thin layers. Thereby, the fine models with RDL etc. in the critical locations were built in ANSYS and analyzed under mechanical shock loading of 2000G in 0.5ms. The stress in the RDL under the critical solder joints were compared when the device was in different locations and the effect of RDL was illustrated. On the basis of the above analysis, the suggestions for improving the reliability of WLCSP with RDL were proposed.
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