Reliability of RDL structured wafer level packages

Jia, Xingli; Yang, Donglun; Bai, Lin; Zhai, Xinduo; Xiao, Fei; Guo, Hongyan; Zhang, Li; Lai, Chi Ming

doi:10.1109/icept.2013.6756634

Cited by 8 publications

(6 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…On the other hand, during a negative thermal loading (∆T< 0), crack gets developed between the RDL wall and the passivation layer wherein the signal enters into the RDL. It primarily induces a cooling capacitance (Ccool) that is a function of crack dimension of the TSV and can be depicted as (6). 2.…”

Section: D) Capacitancementioning

confidence: 99%

“…Notably, a lower prescribed reliability indicator is associated with a higher estimated lifetime of the RDL layer. Furthermore, the research carried in [6][7][8] proposed a RDL-structured wafer-level packaging (WLP) device that is employed in thermal shock tests to study the failure modes related to RDL. Additionally, it is also revealed that the reliability of WLP devices with RDL structures is greatly challenged as the pitch size goes down and the RDL structure affects the thermo mechanical performance of the solder joints on silicon chips, thus causing unexpected failure.…”

mentioning

confidence: 99%

“…It is also more focused towards the design and fabrication of a TSV daisy chain structure, and the analysis using S-parameter and time domain reflectometry (TDR) measurements. While most of the recent research [1][2][3][4][5][6][7][8][9][10] focuses on the fabrication process of RDL, there is a notable lack of attention given to the reliability concerns. This is concerning given the fact that defects and cracks introduced during the service period of RDL can cause stress accumulation and lead to the serious reliability issues.…”

mentioning

confidence: 99%

“…This is concerning given the fact that defects and cracks introduced during the service period of RDL can cause stress accumulation and lead to the serious reliability issues. According to the aforementioned state-ofthe-art research [1][2][3][4][5][6][7][8][9][10], only a few test methodologies are being employed to determine RDL failures by indicators based devices. Although various sizes, layers, and materials have been utilized in the fabrication of RDL along with the interposer, achieving defect-free conditions remains a challenge due to the limited applicability of test methods to specific structure and substrate material.…”

mentioning

confidence: 99%

See 3 more Smart Citations

Impact of Interfacial Crack on Redistribution Layer of TSV based 3D Integration

Kumari

Chandrakar

Majumder

2023

Preprint

View full text Add to dashboard Cite

The interfacial strength of redistribution layer (RDL) and passivation layer plays a crucial role in ensuring the optimal performance and reliability of through silicon vias (TSVs), as it significantly impacts their electrical characteristics and thermal stability, especially in high-density packaging with constrained space. Therefore, it is important to identify and address the interfacial cracks in the RDL that arises due to the factors like manufacturing defects, mechanical stress, and thermal cycling. Neglecting these issues can lead to a range of problems, including reduced device performance, intermittent or complete loss of functionality, and even permanent damage. Owing to ensure their reliability and longevity, this paper introduces for the first time considers the RDL cracks under heating and cooling conditions to model an equivalent electrical circuit and demonstrates the performance in terms of thermal stress, power dissipation, power delay product (PDP), crosstalk delay and power loss. Remarkably, our analysis of interfacial cracked TSV has yielded highly positive results. Specifically, a striking improvement of 22.29% have been observed in case of crosstalk delay, as the minimum crack width of 0.18µm at heating mode approached towards the defect-free condition. A thorough validation of the analytical results reveals an excellent agreement with the EM result, for a negligible deviation of only 3.4% observed in the scattering parameter. This close correspondence between the simulated and quantitative results lends a strong support to the accuracy and reliability of the research findings. Furthermore, this analysis elucidated that the cooling mode is significantly more susceptible to PDP than heating, with a vulnerability that is 7.19% higher at a crack width of 0.18µm.

show abstract

Section: D) Capacitancementioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Impact of Interfacial Crack on Redistribution Layer of TSV based 3D Integration

Kumari

Chandrakar

Majumder

2023

Preprint

View full text Add to dashboard Cite

show abstract

“…An RDL is a layered structure that connects chip pads to external package pads, typically positioned between the chip and the package substrate. However, the connection between the metal lines in the RDL layer and the chip is established through small solder balls or pillars, which can be vulnerable to failure due to thermal stress or other factors [7,8]. The evolution of advanced packaging technology has enabled chips to reach higher levels of integration and performance.…”

Section: Introductionmentioning

confidence: 99%

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

Wang,

Liu,

Huo

et al. 2024

Micromachines

View full text Add to dashboard Cite

With the advancement of Moore’s Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device’s failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging.

show abstract

Adhesion and Interface Studies of the Structure‐Controlled Polyimide with Smooth Copper for High‐Frequency Communication

Zhong

Zhang

et al. 2022

Adv Materials Inter

View full text Add to dashboard Cite

Fan‐out wafer‐level packaging (FOWLP) is expected to become the dominating trend in millimeter wave and 5G communication. However, the reliability faces enormous challenges due to the inherent poor adhesion between the insulating layer of polyimide (PI) and copper wirings in FOWLP. Herein, adhesive polyimide (API) with improved adhesion on smooth Cu by the introduction of benzimidazole and siloxane structure is reported. The results prove that the adhesion strength is increased by 191.46% compared with the conventional PI, owing to the generation of Cu complexes by benzimidazole as well as the cooperation of the flexible siloxane segments. Besides, the APIs not only hold a proper coefficient of thermal expansion (CTE) of 6.28 × 10−6 K−1 matching with Si wafers (2.5 × 10−6 K−1), but also possess CTE (18.56 × 10−6 K−1) of API‐3 matching with Cu circuits (17 × 10−6 K−1), so that a low residual stress of −1.849 MPa is obtained. Moreover, superior mechanical, thermal properties are also obtained, of which the modulus and tensile strength are 6.31 GPa and 170 MPa, while Tg and T5% are as high as 474.6 and 524.57 °C, respectively. Therefore, the as‐prepared high‐performance APIs can be prospective candidates in FOWLP for high‐frequency communication.

show abstract

Reliability of RDL structured wafer level packages

Cited by 8 publications

References 7 publications

Impact of Interfacial Crack on Redistribution Layer of TSV based 3D Integration

Impact of Interfacial Crack on Redistribution Layer of TSV based 3D Integration

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

Adhesion and Interface Studies of the Structure‐Controlled Polyimide with Smooth Copper for High‐Frequency Communication

Contact Info

Product

Resources

About