ONOS discovers and manages a topology made of Transponders and a dedicated OLS, using standard protocols (NETCONF/RESTCONF) and models (OpenConfig/TAPI). The demo is a joint collaboration, towards production deployment, between 3 operators and 2 equipment vendors.OCIS codes: (060.0060) General; (060.4250) Networks
OverviewThe demo shows the use of ONOS (i.e., Open Network Operating System) controller for the control of a partially disaggregated network. The demo has two phases, first topology discovery and second, point-to-point connectivity setup. The demo scenario, including the optical devices and the Open Line System (OLS) is described in figure 1.
Figure 1, TopologyThe underlying infrastructure comprises two disaggregated white box optical transponders considering a partial disaggregation of transponders and Optical Line System (OLS), but considering the transceivers at both ends belonging to the same vendor. The transponders serve as both input and output of the network. Both Transponder client side ports are connected to a virtual host that is capable of generating and receiving L3 traffic. Providing physical connectivity between the two transponders there is an OLS to which both line-side ports of the controller are connected. TAPI Connectivity requests are going to be issued by the operator's BSS or OSS, the system overarching the whole network deployments.The demo and the ODTN are a collaboration between the Open Networking Foundation (ONF), two of its Service Providers: NTT Communications and Telefonica.
This paper reports the first demonstration of a multi-Terabit IP optical router. A sub-equipped rack-mounted prototype has been designed and assembled, demonstrating all key functions of large, scalable packet router. The design exploits burst switching techniques through to an integrated optical packet switching fab ric.
IntroductionFuture routers for IP core networks will soon cross the Terabit capacity barrier, requiring vendors to investigate new architectures and technologies. In this paper, we report implementation of a rack-mounted prototype, assembled as a proofof-concept for a scalable multi-Terabit IP optical router (TIPOR). The design is based on the new technique of burst switching coupled to an optical packet switching fabric. The technology building blocks, the design and techniques used to implement the optical packet switching matrix have been reported in [1][2]. This paper reports the final implementation and analysis of all functionalities, including burst assembly, switch control and scheduling, framers/transceivers and optical switching matrix. The viability of the approach is assessed showing experimental and simulation results.
Concept descriptionCurrent approaches to implement terabit routers consist of using parallel, multi-stage architectures switching small internal cells. We have investigated the feasibility of another approach based on a single-stage optical switching fabric and a larger switched granularity called a burst, which consists of aggregation of IP packets (or ATM cells). This concept has advantages: -relaxed requirements for processing speed: aggregation into bursts allows increase of data rate and scalability of the fabric and router capacity with limited impact on control; -relaxed switch arbitration and contention management: it is expected that a single-stage Time-Space-Time swi tch should be simpler to handle. Adapted algorithms have been developed to study scalability and complexity of the process. In particular, the latency can be reduced due to limited buffers in cascade. -expected higher robustness due to simpler of the fabric structure, limited number of components, simpler monitoring. To implement a single stage core switch, we adopted an optical switching matrix, as opposed to electronics, for these reasons: -relaxed interconnection problems, as bit-rate increases, due to the advantage of optics in this respect. In fact, an optical switching matrix represents the natural extension of passive optical interconnects widely used; -wire-speed switching of packets without parallel demultiplexing, as with electronics, scalable to future higher bit rates;
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