A simple and fast parallel round-robin arbiter for high-speed switch control and scheduling

Zheng, S. Q.; Yang, Mei; Blanton, J.; Golla, P.; Verchere, Dominique

doi:10.1109/mwscas.2002.1186951

Cited by 18 publications

(17 citation statements)

References 11 publications

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“…To implement the central scheduler, one can use the scheduler architecture shown in Figure 4, in which each input/output is associated with an arbiter, which is responsible for selecting one out of N requests. Each arbiter can be implemented by the parallel round-robin arbiter proposed in [16], which has O(log N )-gate delay. Hence, the first stage of the HDS algorithm can be implemented in O(log 2 N )-gate delay.…”

Section: Hardware Implementation Schemementioning

confidence: 99%

Hierarchical scheduling for DiffServ classes

Yang

Wang

et al.

IEEE Global Telecommunications Conference, 2004. GLOBECOM '04.

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Abstract-Due to its simplicity and scalability, the differentiated services (DiffServ) model is expected to be widely deployed across the Internet. For each DiffServ compliant router, the scheduling algorithm is critical in implementing per hop behaviors (PHBs), according to which packets are forwarded. In this paper, we propose the hierarchical DiffServ scheduling (HDS) algorithm to support DiffServ classes on input-queued switches. The proposed HDS algorithm features in a hierarchical scheduling scheme that consists of two levels of schedulers. One level is the central scheduler which is designed to maximize the switch throughput by computing a maximal size matching between input ports and output ports. The other level is formed by input port schedulers which provide differentiated services by serving cells belonging to different classes dynamically. Using such a hierarchical scheme, the implementation complexity and the amount of information needs to be transmitted between input ports and the central scheduler are dramatically reduced compared with existing maximal weight matching based DiffServ scheduling algorithms. The tradeoff of its slightly worse delay performance is acceptable.

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Section: Hardware Implementation Schemementioning

confidence: 99%

Hierarchical scheduling for DiffServ classes

Yang

Wang

et al.

IEEE Global Telecommunications Conference, 2004. GLOBECOM '04.

Self Cite

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“…[4], [10], [13] and [18]). These works focused on n-to-1 arbitration, where a request vector ('1' means a request) of n-bits is given, and an n-bit grant vector is generated with only one granting signal among n bits.…”

Section: Introductionmentioning

confidence: 99%

“…In cases of crossbar network applications ( [4], [13] and [18]), the grant vector is used to configure the switches to connect input ports to output ports. Communication (moving data from input to output port) follows switch configuration.…”

Section: Introductionmentioning

confidence: 99%

“…N-bit arbiter circuits in each of [10], [13] and [18], were built in a tree structure, using 2-input or 4-input primitives. Critical delay path, which influences latency directly, extends from leaves to the root ( [10]) and in some cases, from leaves to the root and then back to leaves ( [13], [18]). [4] proposes a two-level design to reduce latency, which may work well for high number of inputs (n>2), however for 2-input arbiters a single level of logic gates would be sufficient.…”

Section: Introductionmentioning

confidence: 99%

“…The arbiters, proposed in [4] and [13] are based on priority encoder circuits. Priority encoders are simpler and faster, compared to circuits in [10] and [18]; however, they require support of extra circuits to provide fairness among requesting inputs. The above n-to-one arbiter circuits are not as useful for our purpose of implementing the pipelined binary tree.…”

Section: Introductionmentioning

confidence: 99%

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Arbitrate-and-move primitives for high throughput on-chip interconnection networks

Balkan

Vishkin

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18µm technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 GigaRequests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.

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High-performance Packet Switching Architectures

Elhanany¹,

Hamdi²

2007

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The use of registered names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant laws and regulations and therefore free for general use.The publisher makes no representation, express or implied, with regard to the accuracy of the information contained in this book and cannot accept any legal responsibility or liability for any errors or omissions that may be made.

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A simple and fast parallel round-robin arbiter for high-speed switch control and scheduling

Cited by 18 publications

References 11 publications

Hierarchical scheduling for DiffServ classes

Hierarchical scheduling for DiffServ classes

Arbitrate-and-move primitives for high throughput on-chip interconnection networks

High-performance Packet Switching Architectures

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