In vivo, chronic neural recording is critical to understand the nervous system, while a tetherless, miniaturized recording unit can render such recording minimally invasive. We present a tetherless, injectable micro-scale opto-electronically transduced electrode (MOTE) that is ∼60µm × 30µm × 330µm, the smallest neural recording unit to date. The MOTE consists of an AlGaAs micro-scale light emitting diode (µLED) heterogeneously integrated on top of conventional 180nm complementary metal-oxide-semiconductor (CMOS) circuit. The MOTE combines the merits of optics (AlGaAs µLED for power and data uplink), and of electronics (CMOS for signal amplification and encoding). The optical powering and communication enable the extreme scaling while the electrical circuits provide a high temporal resolution (<100µs). This paper elaborates on the heterogeneous integration in MOTEs, a topic that has been touted without much demonstration on feasibility or scalability. Based on photolithography, we demonstrate how to build heterogenous systems that are scalable as well as biologically stable-the MOTEs can function in saline water for more than six months, and in a mouse brain for two months (and counting). We also Manuscript
The neural network enables efficient solutions for Nondeterministic Polynomial-time (NP) hard problems, which are challenging for conventional von Neumann computing. The hardware implementation, i.e., neuromorphic computing, aspires to enhance this efficiency by custom hardware. Particularly, NP hard graphical constraint optimization problems are solved by a network of stochastic binary neurons to form a Boltzmann Machine (BM). The implementation of stochastic neurons in hardware is a major challenge. In this work, we demonstrate that the high to low resistance switching (set) process of a PrxCa1−xMnO3 (PCMO) based RRAM (Resistive Random Access Memory) is probabilistic. Additionally, the voltage-dependent probability distribution approximates a sigmoid function with 1.35%–3.5% error. Such a sigmoid function is required for a BM. Thus, the Analog Approximate Sigmoid (AAS) stochastic neuron is proposed to solve the maximum cut—an NP hard problem. It is compared with Digital Precision-controlled Sigmoid (DPS) implementation using (a) pure CMOS design and (b) hybrid (RRAM integrated with CMOS). The AAS design solves the problem with 98% accuracy, which is comparable with the DPS design but with 10× area and 4× energy advantage. Thus, ASIC neuro-processors based on novel analog neuromorphic devices based BM are promising for efficiently solving large scale NP hard optimization problems.
We present the architecture and assembly of a compact, 3D-integrated CMOS-silicon photonic transceiver for DWDM interconnects. The transceiver interleaves 64 parallel wavelength channels enabling energy efficient scaling of multi-Tbps/mm2 bandwidth densities for future co-packaged chipsets.
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