The authors apply the conductance method at 25 and 150°C to GaAs–Al2O3 metal-oxide-semiconductor devices in order to derive the interface state distribution (Dit) as a function of energy in the bandgap. The Dit is governed by two large interface state peaks at midgap energies, in agreement with the unified defect model. S-passivation and forming gas annealing reduce the Dit in large parts of the bandgap, mainly close to the valence band, reducing noticeably the room temperature frequency dispersion. However the midgap interface state peaks are not affected by these treatments, such that Fermi level pinning at midgap energies remains.

We will shortly review the basic physics of charge-carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high-temperature capacitance-voltage ͑C-V͒ measurements are necessary for GaAs metaloxide-semiconductor characterization. The midgap trapping states in GaAs have characteristic emission times on the order of 1000 s, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the midgap traps possible with standard C-V measurements. C-V characterizations of GaAs/Al 2 O 3 , GaAs/Gd 2 O 3 , GaAs/HfO 2 , and In 0.15 Ga 0.85 As/Al 2 O 3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to midgap energies, an electron trap peak close to midgap energies, and an electron trap peak close to the conduction band.In the past few years a growing interest in passivation of III-V surfaces has emerged again. Several problems exist, nevertheless, with the characterization of these interfaces, leading to some confusion in the literature. These problems have three main causes: First of all, these interfaces present very high densities of interface states, which leads to weak Fermi level pinning and Fermi level pinning behavior at the surfaces, phenomena rarely observed at Si surfaces. 1 Also the interface state distributions are quite different from the "U"-shaped Si interface state distributions. 2 Finally, the relatively larger bandgap of some III-V semiconductors as compared to Si leads to time constants of interface traps well above the usual time constants observed at Si interfaces, creating very long time constant phenomena, not observable with routine capacitance-voltage ͑C-V͒ characterization techniques. 3 A possible solution to all of these problems is the photoluminescence intensity characterization technique, 4 which is a fast measurement technique that has the big advantage of being sensitive to the integral of all interface states present at the III-V surface. Some disadvantages are the relative insensitivity of the technique in the range of 10 13 -10 15 interface states/ cm 2 , a range in which the largest majority of III-V interfaces unfortunately reside, as well as the difficulty to extract energy distributions of interface state densities ͑D it ͒. In this contribution we apply a different technique, the conductance method, 5 and we apply it at different temperatures, which allows the extraction of interface state density over the whole bandgap of GaAs or In 0.15 Ga 0.85 As. First, some general theory is presented, followed by the presentation of experimental measurements on different GaAs and InGaAs metal-oxidesemiconductor ͑MOS͒ capacitor samples with Al 2 O 3 , Gd 2 O 3 , and HfO 2 gate dielectrics. Measurement MethodC-V measurements are made on MOS structures. The band diagram of a typical MOS structure is shown in Fig. 1, where a gate vo...

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