Capacitance-voltage characterization of GaAs–Al2O3 interfaces

Abstract

The authors apply the conductance method at 25 and 150°C to GaAs–Al2O3 metal-oxide-semiconductor devices in order to derive the interface state distribution (Dit) as a function of energy in the bandgap. The Dit is governed by two large interface state peaks at midgap energies, in agreement with the unified defect model. S-passivation and forming gas annealing reduce the Dit in large parts of the bandgap, mainly close to the valence band, reducing noticeably the room temperature frequency dispersion. However the midgap interface state peaks are not affected by these treatments, such that Fermi level pinning at midgap energies remains.

Influence of Atomic Layer Deposition Temperatures on TiO2/n-Si MOS Capacitor

“…Errors in the capture cross section by three orders of magnitude only made 0.18 eV energy difference within the bandgap of the semiconductor. 24 The trap level can be identified as the energy position from the frequency at which G p /ω is maximum. Also, based on the maximum conductance from the measurement, an approximate equation to calculate interface trap density is given by:…”

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

“…GaAs MOS devices generally exhibit poor performance owing to electron trapping at the gap states, thus preventing effective modulation of the surface Fermi level. 5,6,9 As pointed by Robertson et al, though a perfect trivalent oxide/GaAs interface is free of gap states, the presence of specific interface defects, As-As dimers, and dangling bonds of Ga and As contributes to the formation of important gap states. [10][11][12][13][14] This understanding strongly suggests that the elimination or passivation of these defect states is mandatory to bring out superior transport properties of GaAs.…”

“…Both the n-and p-type capacitors, with a thin AlN layer (t AlN 30 s), exhibited well-behaved C-V characteristics in contrast to conventional Al 2 O 3 /GaAs systems. 9 The corresponding n-type capacitors generally display large frequency dispersions, resulting in a nearly zero accumulation capacitance at 1 MHz. Contrarily, as observed in the current systems, the presence of a thin AlN passivation layer significantly reduced the frequency dispersion of accumulation capacitance (referred as "accumulation dispersion") of the corresponding n-type capacitor.…”

“…Although Al 2 O 3 /GaAs MOS devices prepared using ALD display good performance, 7,19 these devices still have many interface defects. 9 A promising route to modifying and improving such interfaces is via the preparation of an interface passivation layer, such as sulfide, silicon, phosphide, or nitride layer, 7 while combining an ALD-based dielectric formation process. Recently, nitrogen passivation has attracted strong interest for improving dielectric/III-V interfaces.…”

“…Energy distributions of D it for the dielectric/GaAs interface were extracted based on the conductance method 9,[40][41][42] from the corresponding C-V and G-V data obtained at various temperatures. Each D it value was calculated assuming 43 where q is the charge of an electron, G p is the parallel conductance estimated from the C-V and G-V data, and ω is the measured pulsation.…”