In this work, we propose fully integrated multilayer stacked topology of asymmetrical inductor with patterned ground shield (PGS), which also serves as capacitor. The main aim of the study is efficient usage of limited chip area for integrated passive components by challenging layout properties of asymmetrical integrated inductor and integrated MOS capacitor and enhancing their main electrical properties. Several principles of geometry modifications(vertical and horizontal parallelization, slicing, tapering, equal path lengths) were applied to a four-turn octagonal asymmetrical integrated inductor with the series DC resistance RL = 1.75 Ω and inductance L = 11.66 nH on low frequencies. Remaining area under integrated inductor was used for a capacitor with capacitance CP GS = 1.6 nF and the equivalent series resistance RC = 7.25 Ω. The whole structure was designed in a standard 65nm CMOS technology for use in a switched DC-DC power converter working in MHz-range for a Photovoltaic (PV) Energy Harvester (EH).
This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is builtin with the calibrated FDDA circuit, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, and process corners and ageing analyses performed for the temperature range from -20°C to 85°C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 µV to 167 µV). The concept proposed in this work utilizes advanced high precision calibration algorithm.
This paper presents an overview and State-of-the-Art of fully integrated inductors with common fabrication processes used for implementation of these structures into a chip. The first step is an overview of fabrication technologies that starts with standard CMOS general purpose processes expanded by Far-BEOL and substrate alteration process (SOI, Silicon Embedded, TSV, TGV, PTH, Core Insertion); and continues to advanced process nodes like SMMT and Bond Wire utilization. Then, an overview of fully integrated inductor structures consists of selected topologies with notable parameters achieved in last few years. Critical parameters of integrated inductors include: inductance L DC , inductance density L A , quality factor Q, selfresonant frequency FSR and series resistance R DC . These parameters are as important as the purpose and fabrication process.
In this paper design and function of the fully differential (FD) switched-capacitor (SC) integrator for ultra-low voltage Sigma-Delta analog to digital converter (Σ-∆ ADC) are presented. The proposed integrator was designed for differential input signal and applicable as a main analog block of ultra-low voltage Σ-∆ ADC in standard 130 nm CMOS technology. The main block of proposed integrator is operational transconductance amplifier (OTA) based on two-stage Rail-to-Rail (RtR) FD operational amplifier (OPAMP) working in sub-threshold regime. The characteristic properties of this circuit is non-standard OTA topology, using SC common-mode feedback (CMFB) circuit and using switching T-gates. All of these subcircuits are supplied by only 0.6 V with achieved gain 24.09 dB and cutoff frequency 165.95 kHz.
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