Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

A design analysis of a telecentric microchannel relay system developed for use with a smart-pixel-based photonic backplane is presented. The interconnect uses a clustered-window geometry in which optoelectronic device windows are grouped together about the axis of each microchannel. A Gaussian-beam propagation model is used to analyze the trade-off between window size, window density, transistor count per smart pixel, and lenslet ƒ-number for three cases of window clustering. The results of this analysis show that, with this approach, a window density of 4000 windows/cm(2) is obtained for a window size of 30 µm and a device plane separation of 25 mm. In addition, an optical power model is developed to determine the nominal power requirements of a 32 × 32 smart-pixel array as a function of window size. The power requirements are obtained assuming a complementary metal-oxide semiconductor inverter-amplifier and dual-rail multiple-quantum-well self-electro-optic-effect devices as the receiver stage of the smart pixel.

This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED techinology uses CMOS silicon circuitry with GaAs-AIGaAs multiple-quantumwell modulators and detectors. The chip has been designed based on the Hyperplane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given.

Due to their low power consumption, high modulation speed, and low cost, vertical-cavity surface-emitting lasers (VCSEL) dominate short-reach data communications as the light source. In this paper, we propose a compact equivalent circuit model with noise effects for high-speed multi-quantum-well (MQW) VCSELs. The model comprehensively accounts for the carrier and photons dynamisms of a MQW structure, which includes separate confinement heterostructure (SCH) layers, barrier (B) layers, and quantum well (QW) layers. The proposed model is generalized to various VCSEL designs and accommodates a flexible number of quantum wells. Experimental validation of the model is performed at 25 Gb/s with a self-wire-bonded 850 nm VCSEL.

We describe the design and implementation of a free-space optical interconnect for multi-processor and backplane applications. The system is designed to interconnect 4 nodes in a unidirectional ring, with a total of 256data channels propagating from node to node. Each node contains an array 5 12 GaAs electro-absorption modulators and 512 photodetectors, hybridly attached to a silicon integrated circuit. Light is relayed between nodes with a rigid micro-optical system. System results are presented.