The thermal stability of flip-chip solder joints made with trilayer Al/Ni(V)/Cu underbump metalization (UBM) and eutectic Pb-Sn solder connected to substrates with either electroless Ni(P)-immersion gold (ENIG) or Pb-Sn solder on Cu pad (Cu-SOP) surface finish was determined. The ENIG devices degraded more than 50 times faster than the Cu-SOP devices. Microstructural characterization of these joints using scanning and transmission electron microscopy and ion beam microscopy showed that electrical degradation of the ENIG devices was a direct result of the conversion of the as-deposited Ni(V) barrier UBM layer into a porous fine-grained V 3 Sn-intermetallic compound (IMC). This conversion was driven by the Au layer in the ENIG surface finish. No such conversion was observed for the devices assembled on Cu-SOP surface finish substrates. A resistance degradation model is proposed. The model captures changes from a combination of phenomena including increased (1) intrinsic resistivity, (2) porosity, and (3) electron scattering at grain boundaries and surfaces. Finally, the results from this study were compared with results found in a number of published electromigration studies. This comparison indicates that degradation during current stressing in the Pb-Sn bump/ENIG system is in part due to current-crowding-induced Joule heating and the thermal gradients that result from localized Joule heating.
Eight commercial semiconductor grade epoxy compounds that are used to encapsulate 1C (integrated circuit) devices have been evaluated for their ability to minimize the development of thermal stresses which can cause failure during device temperature cycling. Thermal expansion, dynamic modulus and adhesion studies are used to describe the mechanical interaction between the plastic package and the silicon device it surrounds. A “figure of merit” is defined for the development of stress on the 1C device as it is cooled after the packaging process. The stress is shown to be proportional to the product of three terms: (αp‐αs) Ep (Tanch‐T) where αp and αs are the expansion coefficients for the plastic and silicon, respectively, Ep is the modulus of the epoxy and Tanch is the temperature at which the epoxy becomes anchored to the silicon device during transfer molding. In addition, the importance of good adhesion between the epoxy encapsulant and the silicon device to prevent package cracking has been demonstrated by finite element analysis and a novel adhesion test.
In this study, the wire-sweep problem has been studied by performing experiments using a commercial-grade epoxy molding compound, a real chip assembly, and an industrial encapsulation process. After encapsulating the chip, the deformed wire shape inside the plastic package has been determined by X-ray scanning. A procedure for the wire-sweep calculation during encapsulation process has been developed. The wire sweep values have been calculated using this procedure with material properties measured from experiments. The calculated wire-sweep values are compared with experimental values measured at different mold temperatures, fill times, and cavities. In most cases, the calculated values are in good agreement with the experimental values.
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