Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, ultra high level of integration mandates design of systems-on-chip that encompass nuinerous intra-synchronous blocks with decreased functional granularity and increased communication demands. To address these issues we have developed an on-chip bus network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design. The approach has three components: a communication profiler, a bus network designer, and a fast approximate floorplanner. The communication profiler collects run-time informat,ion about the traffic between system cores. The bus network dcsign componcxit optimixcs thc bus network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan and to communicate information about the most constrained parts of the network. 1 lntrodiiction Due to design coniplcsit,y and tiine-to-mark(:t prcssurc, it is expected that futurc systems-on-chip arc dcsigned its networks of virtual components. Virtual componexit (VC) is a core wrapped with logic that enables it to 1 / 0 dat,iL to the attached bus with an nr1,itrary bus protocol 171. Bwause
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