This paper presents a 3D transmission line matrix implementation(TLM) for the solution of transient heat flow in integrated semiconductor devices. The implementation uses a rectangular discontinuous mesh to allow for local mesh refinement. This approach is based on a quad tree meshing technique which can have a complex geometry using blocks of varying sizes. Each such block can have a maximum of two adjacent blocks on any vertical side and a maximum of four blocks on the top or bottom.The TLM implementation is based on a physical extraction of a resistance and capacitance network and then the creation of the appropriate TLM matrix. The formulation allows for temperature dependent material parameters and a non-uniform time stepping.The simulator is first tested using a 2D example of a heat source in a rectangular region. Using this example the numerical error is determined and found to be less than 0.4%. Next, nonlinearities are included, and a number of non-uniform time stepping algorithms are tested. Then, a 3D problem is also compared to an analytical solution and again the error is very small. Finally, an example of a full solution of heat flow in a realistic Si trench device is presented.
This paper presents a new approach to compact thermal modeling. The paper shows how a parametrized reduced thermal model of an IC component can be created based on a parametric model reduction technique. By applying this technique, a large system of equations characterizing a discretized fully detailed numerical thermal model can be drastically reduced. The final product of a parametrized model reduction procedure is a set of small matrices presenting an abstract description of the component thermal behavior. The reduced system can be used to either synthesize a resistive network or formulate a set of connection equations to be connected to higher simulation levels. External boundary conditions are parameters of the reduced model and can be specified at simulation time. A parametrized reduced thermal model is found to have a number of advantages over an optimized resistor network model. The model can be generated quickly (one lower-upper (LU) decomposition is needed), high accuracies are obtained with a typical error of less than 0.1%. The technique also predicts temperatures at all internal nodes of the original detailed model, not just a single junction temperature. In this paper, the new technique is demonstrated through two examples of realistic IC components: a GaAs power amplifier and a generic multichip module ball grid array package. Both reduced models are connected to substrates in a number of different configurations. Thermal analysis performed in each case shows the importance of the geometric configuration of the connections on predictive capability. Index Terms-GaAs power amplifier, model reduction, multichip module ball grid array (MCMBGA), parametrized thermal compact model, thermal modeling.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.