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Thin film barium strontium titanate (BST) shows great promise for voltage tunable dielectric devices for use at RF and microwave frequencies. An MOCVD process has been developed for production of BST, resulting in films with very low losses (as low as 0.002-0.004) and tunabilities over 50% at low operation voltages. With these values of BST loss, overall device quality factors at RF (100 MHz+) frequencies are primarily limited by losses in the thin metal electrodes, such as Pt, normally used for ferroelectric thin films. The bottom electrode in parallel plate capacitor structures is particularly challenging, since it must provide a good growth surface for BST and be stable at high (>600 "C) growth temperatures in an oxidizing atmosphere yet have high conductivity and compatibility with Si or SiO2/Si substrates. These challenges have previously prevented use of Pt thicknesses over 0.1-0.2 pm. Our solution to this problem, involves combinations of adhesion layers at the Pt/SiO2 interface and embedded stabilization layers to make functioning Pt bottom electrodes as thick as 2 pm. Devices with dielectric Q factors over 150 at 100 MHz (tan 6 -0.006 as measured and modeled by S-parameters) and overall device Q factors over 50 at 30 MHz are described. We have also inserted these devices into tunable filters, achieving tunabilities of 50% and low insertion losses (0.3 dB) at RF frequencies.

Composite metallization stacks consisting of 1.5 µm W layers and 0.1 µm Ir layers have been developed for low series resistance electrode applications. These hybrid metallization layers are compatible with barium strontium titanate deposition and standard patterning/etching procedures. The multilayer stacks were prepared for use as bottom electrodes in microwave varactors based upon the electrically tunable dielectric barium strontium titanate. These low resistivity layers are critical for realizing low insertion loss devices, and overcome difficulties associated with delamination or hillocking in traditional noble metal layers. Controlling the oxygen content during BST deposition was necessary to achieve high-quality BST and a stable electrode stack. Using these metallization stacks and optimized deposition conditions, BST films with tan δ values below 0.007 and tunabilities of 2:1 were realized. These properties are comparable to those measured on typical Pt/BST/Pt/SiO 2 /Si capacitors. Finally, a combination of reactive ion and wet chemical etching were used to demonstrate that the thick hybrid metallization layers are patternable using routine and manufacturable process methods.

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To achieve 65 nm technology node requirements, CMP processes must provide improved control of selectivity, topography, wire cross section, and process robustness. Slurries and processes must also be compatible with fragile low k materials by providing low erosion and shear forces. We present data on a unique step 1 bulk Cu removal slurry with high selectivity, removal rates over 8000 Å/min, and extremely low liner removal/erosion in high (90%) density structures. This is achieved through a combination of surface modified abrasives and alternative inhibitors which provide superior performance and reduced electrochemical activity compared to benzotriazole, a commonly used inhibitor. The step 1 slurry was used with a step 2 liner removal slurry that can be chemically tuned to adjust relative selectivities of Cu:Ta:oxide from the nominal ratio of 1:0.9:1.6, allowing its use with a variety of integration schemes. Results of CMP planarization experiments on 200 mm blanket and patterned single damascene test wafers are described, including electrical data which demonstrates low overpolish sensitivity.