PurposeThe purpose of this paper is to examine the microstructure and evaluate the intermetallic compounds in the following lead‐free solder alloys: Sn98.5Ag1.0Cu0.5 (SAC105) Sn97.5Ag2.0Cu0.5 (SAC205) Sn96.5Ag3.0Cu0.5 (SAC305) and Sn95.5Ag4.0Cu0.5 (SAC405).Design/methodology/approachX‐ray diffraction (XRD) and scanning electron microscopy (SEM) were employed to identify the main intermetallics formed during solidification. Differential scanning calorimetry (DSC) was used to investigate the undercooling properties of each of the alloys.FindingsBy using XRD analysis in addition to energy dispersive spectroscopy (EDS) it was found that the main intermetallics were Cu6Sn5 and Ag3Sn in a Sn matrix. Plate‐like ε‐Ag3Sn intermetallics were observed for all four alloys. Solder alloys SAC105, SAC205 and SAC305 showed a similar microstructure, while SAC405 displayed a fine microstructure with intermetallic phases dense within the Sn matrix.Originality/valueCurrently, low‐silver content SAC alloys are being investigated due to their lower cost, however, the overall reliability of an alloy can be greatly affected by the microstructure and this should be taken into consideration when choosing an alloy. The size and number of Ag3Sn plate‐like intermetallics can affect the reliability as they act as a site for crack propagation.

Precision thick chip resistors are used in a variety of different industries, from telecommunications to automotive electronics, and as such can be exposed to mild and aggressive corrosive environments. This paper investigates the corrosion performance of two generic precision thick chip resistors in a controlled corrosive atmosphere consisting of 60 C, 4 ppm H 2 S and water vapor in purified air. The resistors were exposed in an environmental chamber for periods of 5, 10, 15, 30, and 60 days. Following exposure, the samples were cross sectioned and subjected to surface analysis using microscopy and microanalysis. After the initial stages of exposure, corrosion was observed on only one of the two types of resistors. The corrosion developed because H 2 S gas and water vapor diffuses through the thin protective organic layer on the resistor, and subsequently reacts with the silver conductor layer. Corrosion was facilitated by poor overlapping of the solder and nickel layer and, in particular the glass binder over the glass overcoat, which allowed silver and sulphur to diffuse along the interface. In addition, this poor overlapping allowed contact between the nickel layer and the silver layer resulting in the development of an electrochemical corrosion cell. The main corrosion products that developed were silver sulfide (Ag 2 S) and nickel sulphur residue.Index Terms-Atmospheric corrosion, precision thick chip resistors, printed circuit board (PCB), silver sulphide (Ag 2 S).

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Pure copper samples were exposed in an environmental chamber for 2, 4, 7, 15, and 30 days at 90% relative humidity, 40°C, and 4 ppm hydrogen sulfide ͑H 2 S͒. Samples were subsequently subjected to microscopy and microanalysis using different techniques: scanning electron microscopy, energy analysis dispersive X-ray spectroscopy, X-ray diffraction, focused ion beam ͑FIB͒, and secondary ion mass spectroscopy. The corrosion samples were cross sectioned and the different corrosion layers were imaged using FIB. After 30 days exposure the predominant corrosion products were copper sulfide ͑Cu 2 S͒ and cuprite ͑Cu 2 O͒. Once the Cu 2 S reached a minimum thickness, the rate of growth of the layer became parabolic due to the limiting Cu + diffusion through a thickening film. As the layers reach a critical thickness ͑ϳ1000 nm͒ internal stresses and defects in the corrosion layer allow virtually free access of H 2 S and O to the underlying layers, consequently accelerating the film growth.

There is considerable reported evidence that a large percentage of failures which afflict portable electronic products are due to impact or shock during use. Failures of the external housing, internal electronic components, package-to-board interconnects, and liquid crystal display panels may occur as the result of accidental drops. Moreover, the introduction of lead-free solder to the electronics industry will bring additional design implications for future generations of mobile electronic systems. In this paper, drop tests performed on PCBs populated with ball grid arrays (BGAs) are reported. During testing, measurements from strain gages were recorded using a high-speed data acquisition system. Electrical continuity through each package was monitored during the impact event in order to detect failure of package-to-board interconnects. Life distributions were established for both a lead-free and a tin-lead solder for various drop heights. In addition, failure analysis was carried out using microsection techniques, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS). Resistance measurements throughout the drop event indicated that different failure mechanisms occurred for different drop heights. The explicit finite element (FE) method was employed to evaluate the peel stress at the critical solder joint and a stress-life model is then established for the lead-free solder. The maximum peel stress location was found to match the location of failure initiation revealed from the failure analysis. It was also discovered that, for board level drop testing, that there is a considerable difference between the lead-free solder characteristic life and the tin-lead solder characteristic life.