In this article, we propose new approaches for solving the useful-skew tree (UST) routing problem [Xi and Dai 1997]: clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for the zero-skew tree (ZST) [Edahiro 1992;Chao et al. 1992] and bounded-skew tree (BST) [Cong and Koh 1995;Huang et al. 1995;Kahng and Tsao 1997;Cong et al. 1998] routings; hence, the names UST/DME and Greedy-UST/DME for our UST algorithms. Our novel contribution is that we simultaneously perform skew scheduling and tree routing so that each local skew range is incrementally refined to a skew value that minimizes the wirelength increase during the bottomup merging phase of DME. As a result, not only is the skew schedule feasible, but also the wirelength increase is minimized at each merging step of clock tree construction. The experimental results show very encouraging improvement over the previous BST/DME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total routing wirelength.

Stochastic hill-climbing algorithms, particularly simulated annealing SA and threshold acceptance TA, have become very popular for global optimization applications. Typical implementations of SA or TA u s e monotone temperature or threshold schedules, and are not formulated to accommodate practical time limits. We present a new threshold acceptance strategy called Old Bachelor Acceptance OBA which has three distinguishing features: i it is specifically motivated by the practical requirement of optimization within a prescribed time bound, ii the threshold schedule is self-tuning, and iii the threshold schedule is non-monotone, with threshold values even allowed to become negative. The standard implementation of the TA method of Dueck and Scheuer is a special case of OBA. Experiments using several classes of symmetric traveling salesman problem instances show that OBA can outperform previous hillclimbing methods for time-critical optimizations. A number of directions for future work are suggested.Give n a s e t S of feasible solutions and a real-valued cost function f : S ! , global optimization may without loss of generality be formulated as the search for a global minimizer s 2 S such t h a t f s f s 0 8s 0 2 S. T ypically, jSj is very large compared to the number of solutions that can be examined in practice. For small instances of certain global optimizations, implicit enumeration e.g., branch-and-bound or polyhedral approaches can prune the solution space and a ord solutions within practical time limits; other problem formulations may be tractable to problem-speci c methods. However, many important global optimization formulations both discrete and continuous are not only NP-hard 8 , but also have no known problem-speci c solution methods. Therefore, generalpurpose heuristics are of interest. In this paper, we present a new class of stochastic hill-climbing heuristics for global optimizations; we call this new strategy Old Bachelor Acceptance OBA.Our discussion opens in Section 1 with a characterization of iterative, stochastic hill-climbing heuristics; these are usually superior to greedy methods in that they can probabilistically escape from locally optimal solutions. The leading examples of stochastic hill-climbing algorithms the simulated annealing SA approach of Kirkpatrick et al. 25 and Cerny 6 , along with the threshold acceptance approach o f D u e c k and Scheuer 7 h a ve gained wide popularity due to the quality o f t h e 1

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Abstract-This paper presents new single-layer, i.e., planarembeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called Planar-DME, consists of two parts. The first algorithm, called Linear-Planar-DME, guarantees an optimal planar zero-skew clock tree (ZST) under the linear delay model. The second algorithm, called Elmore-Planar-DME, uses the Linear-Planar-DME connection topology in constructing a low-cost ZST according to the Elmore delay model. While a planar ZST under the linear delay model is easily converted to a planar ZST under the Elmore model by elongating tree edges in bottom-up order, our key idea is to avoid unneeded wire elongation by iterating the DME construction of ZST and the bottom-up modification of the resulting nonplanar routing. Costs of our planar ZST solutions are comparable to those of the best previous nonplanar ZST solutions, and substantially improve over previous planar clock routing methods. I. PRELIMINARIESHE PLACEMENT phase of physical layout determines positions for the synchronizing elements of a circuit, which are the sinks of the clock net. Large cell-based designs can have thousands of sinks in a clock net, with these sinks located quite arbitrarily throughout the layout region. We denote the set of sink locations in a clock routing instance as S = {SI, 5-2, . . . , s,} c 9'. A connection topology is a rooted binary tree, G, with n leaves corresponding to the sinks in S. A clock tree T ( S ) is an embedding of the connection topology in the Manhattan plane, i.e., a placement in 9' which assigns each internal node v E G to a location which we denote as I (T, U ) , or more simply as I ( U) when no confusion arises. The root of the clock tree is the source, denoted by SO. When the clock tree is rooted at the source, any edge between a parent node p and its child U may be identified with the child node, i.e., we denote this edge as e,. In our discussion, the distance between two points p and q is the Manhattan distance d ( p ; q ) , and the distance between two sets of points P and Q, d(P, Q), is min{d(p, q)Ip E P and q E Q}. The cost of the edge e, is simply its wirelength, denoted le,l; this is always at least as large as the Manhattan distance between the endpoints of the edge, i.e., levlis the total wirelength of the edges in T ( S ) . ( S ) is zero then T ( S ) is a zero-skew tree (ZST). In what follows, we address the Zero Skew Clock Routing Problem: Given a set S of sink locations, construct a ZST T ( S ) with minimum cost. A. Minimum-Cost Zero-Skew TreesIn the IC CAD literature, minimum-cost, exact zero-skew clock trees for cell-based designs have been constructed by applying geometric optimizations over the set of sink locations. The associated formulations are perhaps best motivated by the "monolithic" single-buffer clocking approach [2], [ 101. From the circuits/systems perspective, workers such as Friedman [ 141 have considered these geometric methods as "subroutines" in addressing further concerns su...

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