Ust/Dme

Abstract

In this article, we propose new approaches for solving the useful-skew tree (UST) routing problem [Xi and Dai 1997]: clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for the zero-skew tree (ZST) [Edahiro 1992;Chao et al. 1992] and bounded-skew tree (BST) [Cong and Koh 1995;Huang et al. 1995;Kahng and Tsao 1997;Cong et al. 1998] routings; hence, the names UST/DME and Greedy-UST/DME for our UST algorithms. Our novel contribution is that we simultaneously perform skew scheduling and tree routing so that each local skew range is incrementally refined to a skew value that minimizes the wirelength increase during the bottomup merging phase of DME. As a result, not only is the skew schedule feasible, but also the wirelength increase is minimized at each merging step of clock tree construction. The experimental results show very encouraging improvement over the previous BST/DME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total routing wirelength.

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network

“…The skew specification can also be expressed as the delay target for each register directly. A clock distribution network, which is usually a tree rooted at the clock source, is constructed through clock routing [21] for a given register placement and skew specification, such that the skew specification is satisfied. The skew scheduling and clock routing procedures can also be integrated together [22].…”

Improved algorithms for link-based non-tree clock networks for skew variability reduction

“…Obtain initial clock tree from any of the available clock tree routing algorithms in the literature like [17,18,20]. 2.…”

Buffered clock tree for high quality IC design

“…The example in Figure 1 illustrates that different merging schemes (abstract trees) may provide different wirelength for non-zero skew clock routing. A few works [13,14] integrate skew scheduling with clock routing to exploit the useful skews. Starting with a zero skew routing tree, the work of [14] performs merging segment perturbation and gate sizing to minimize power consumption subject to setup-time and holdtime constraints for a fixed clock period time.…”