Instruction pressure is the level of time, space, and power required to manage the instruction stream to support highspeed execution of modern multicore general processor and embedded controller based computing. L1 instruction cache and processor pin bandwidth are examples of direct resource costs imposed by the instruction access demand of a processor architecture. This paper explores the potential for reducing instruction pressure through a combination of variable length binary instruction set and Huffman encoding to reduce the average number of bits per instruction compared to a typical fixed-length fixed-code binary instruction set. The PRECISE (Processor Register Extensions for Collapsed Instruction Set Encoding) methodology addresses the data type, opcode, and register access components of the instruction stream. This paper focuses on opcode compression through a set of benchmark-driven experiments to identify clusters of near optimal ISA fits. The results demonstrate that a small number of distinct binary ISAs can provide reasonably good fits across a broad range of application benchmarks.
Abstract-CPU performance is determined by the interaction between available resources, microarchitectural features, the execution of instructions, and by the data. These elements can interact in complex ways, making it difficult for those seeing only aggregate performance numbers, such as miss ratios and issue rates, to determine whether there are reasonable avenues for performance improvement. A technique called instructionlevel visualization helps users connect these disparate elements by showing the timing of the execution of individual program instructions. The PSE visualization program enhances instructionlevel visualization by showing which instructions contribute to execution inefficiency in a way that makes it easy to locate dependent instructions and the history of events affecting the instruction. A simple annotation system makes it easy for a user to attach custom information. PSE has been used for microarchitecture research, simulator debugging, and for instructional use.
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