The design space exploration (DSE) problem addressed in this paper is to find out Multi-Processor System-on-Chip architectures for a given multi-task signal processing application aiming to minimize the system cost while satisfying the real-time constraints. It involves the following three sub-problems: selecting processing elements, mapping an application to the processing elements, and determining the communication architecture. The proposed approach consists of two inner design loops: one is a cosynthesis loop that determines the selection of PEs and the mapping of a given application to the PEs, and the other is a communication architecture synthesis loop to find the hierarchical shared bus architecture. We specify an application with a synchronous data flow (SDF) model of computation that has well-matched semantics with the algorithmic function flow in DSP applications. To solve the problem, we need to compare the estimated performance of design points and choose the best ones. The common method of simulation-based performance estimation is too time-consuming to explore the wide design space. Thanks to the analytical properties of the SDF model, the performance estimation can be done without HW/SW cosimulation in both loops. A global feedback from the communication architecture synthesis step to the cosynthesis step forms the proposed DSE framework. We use a real-life application, 4-channel Digital Video Recorder (DVR) that is a multi-task example, as well as randomly generated graphs to show the viability of the proposed approach.

Existent hardware-software (HW-SW) codesign tools mainly focus on HW-SW cosimulation to build a virtual prototyping environment that enables software design and system verification without need of making a hardware prototype. Not only HW-SW cosimulation, but also HW-SW codesign methodology involves system specification, functional simulation, design-space exploration, and hardware-software cosynthesis. The PeaCE codesign environment is the first full-fledged HW-SW codesign environment that provides seamless codesign flow from functional simulation to system synthesis. Targeting for multimedia applications with real-time constraints, PeaCE specifies the system behavior with a heterogeneous composition of three models of computation and utilizes features of the formal models maximally during the whole design process. It is also a reconfigurable framework in the sense that third-party design tools can be integrated to build a customized tool chain. Experiments with industry-strength examples prove the viability of the proposed technique.

Embedded software design for MPSoC needs parallel programming. Popular programming languages such as C and C++ are not adequate for initial specification since they are designed for sequential execution. Therefore models of computations that express concurrency naturally are preferred for initial specification, among which dataflow model has been widely used to specify signal processing applications. While software generation from SDF specification has been researched extensively, dataparallelism has not been properly considered in the previous work. This paper presents data-parallel code generation technique from SDF graphs. We use OpenMP directives to specify dataparallelism and resort OpenMP compiler to obtain the final target code. Preliminary experimentation with real-life examples shows the viability of the proposed technique.

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The cosynthesis problem addressed in this paper