A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification

Abstract

The design space exploration (DSE) problem addressed in this paper is to find out Multi-Processor System-on-Chip architectures for a given multi-task signal processing application aiming to minimize the system cost while satisfying the real-time constraints. It involves the following three sub-problems: selecting processing elements, mapping an application to the processing elements, and determining the communication architecture. The proposed approach consists of two inner design loops: one is a cosynthesis loop that determines the selection of PEs and the mapping of a given application to the PEs, and the other is a communication architecture synthesis loop to find the hierarchical shared bus architecture. We specify an application with a synchronous data flow (SDF) model of computation that has well-matched semantics with the algorithmic function flow in DSP applications. To solve the problem, we need to compare the estimated performance of design points and choose the best ones. The common method of simulation-based performance estimation is too time-consuming to explore the wide design space. Thanks to the analytical properties of the SDF model, the performance estimation can be done without HW/SW cosimulation in both loops. A global feedback from the communication architecture synthesis step to the cosynthesis step forms the proposed DSE framework. We use a real-life application, 4-channel Digital Video Recorder (DVR) that is a multi-task example, as well as randomly generated graphs to show the viability of the proposed approach.

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study

“…In contrast, more abstract methods based on synchronous data flows (SDFs) [12] are commonly used to model system communication structure and memory hierarchy, allowing for static scheduling and mapping analysis of streaming applications with multiple communicating loop nests. Unfortunately most SDF models do not take into account the multidimensionality of the transferred data, and, consequently, they are not well-suited to describe the effects of loop-transformation-like operations that can be used to efficiently explore the data parallelism of an application.…”

Performance estimation of embedded software with confidence levels

“…Several techniques allow to evaluate the performance of a system. Techniques based on running on real systems or on simulators are usually not suitable to be integrated in an embedded system design flow since they are too slow to be adopted in design space exploration [1]. Also Worst Case Execution Time (WCET) techniques [2] can not be easily integrated in a design space exploration automatic flow: even if they can be implemented in automatic analysis tools, they still require designer interaction (e.g., setting the bounds of loop iterations).…”

Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration

“…This brings the service guarantee from individual access requests to the application level. Ultimately, this allows us to compute the worst-case latency and throughput of applications that run on MPSoCs using dataflow-based system-level design techniques [10], [11]. This paper has two main contributions: (1) a piecewise linear service guarantee for CCSP, which we refer to as birate service guarantee, as shown in Figure 1, and (2) an equivalent dataflow model of the bi-rate service guarantee.…”

“…State-of-theart dataflow-based system-level analysis techniques [10], [11] require various aspects of the system, such as computation, buffers and arbitration, to be modeled with dataflow components. Modeling resource sharing with dataflow components is not trivial, as equivalence in temporal behavior with the service guarantees of the arbiters should be proved using rigorous algebraic steps [26], [27].…”