Data-Parallel Code Generation from Synchronous Dataflow Specification of Multimedia Applications

Kwon, Seongnam; Lee, Choonseung; Ha, Soonhoi

doi:10.1109/estmed.2007.4375810

Cited by 2 publications

(2 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The application is first partitioned for a multi-processor implementation which involves deciding how many cores to use, which core to perform which functions, etc. Examples of such tools are discussed in [9], [11] and [12]. After this stage, codes for each processor as well as the architecture and communication requirements for the NoC are obtained.…”

Section: Introductionmentioning

confidence: 99%

An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee

Yang

Kumar

2010

2010 International Conference on Field-Programmable Technology

View full text Add to dashboard Cite

With an increasing trend to implement Network-onChip (NoC)-based Multi-Processor Systems-on-Chips (MPSoCs), NoCs need to have guaranteed services and be dynamically reconfigurable. Many current NoCs consume too much area and cannot support dynamic reconfiguration. In this paper, we present an area-efficient Spatial Division Multiplexing (SDM)-based NoC. We replaced area consuming 32-bit to M-bit serializers with 32-bit to 1-bit serializers in the network interface and incur almost no loss in performance. We also restrict flexibility in the router to achieve further area reduction. A separate areaefficient control network, with an overhead of 3.9% of the total area of the NoC, is developed to support dynamic reconfiguration.

show abstract

Section: Introductionmentioning

confidence: 99%

An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee

Yang

Kumar

2010

2010 International Conference on Field-Programmable Technology

View full text Add to dashboard Cite

show abstract

“…For this reason, and in contrast to [7], we consider memory access times in our scheduling technique. In [8], a technique is presented to generate a dataparallel schedule from applications modeled as synchronous dataflow graphs. Similar to [7], the authors do not consider the overhead of moving code and data between on-chip and off-chip memory.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling

Damavandpeyma

Stuijk

Basten

et al. 2011

2011 14th Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

Abstract-The ever increasing performance gap between processors and memories is one of the biggest performance bottlenecks for computer systems. In this paper, we propose a task scheduling technique that schedules an application, modeled with a task graph, on a multiprocessor system-onchip (MPSoC) that contains a limited on-chip memory. The proposed scheduling technique explores the trade-off between executing tasks in a code-driven (i.e. executing parallel tasks) or data-driven (i.e. executing pipelined tasks) manner to minimize the run-time of the application. Our static scheduler identifies those task sequences in which it is useful to use a codedriven execution and those task sequences that benefit from a data-driven execution. We extend the proposed technique to consider prefetching when choosing a suitable task order. The technique is implemented using an integer linear programming framework. To evaluate the effectiveness of the technique, we use an application from the multimedia domain and a synthetic task graph that is used in related work. Our experimental results show that our scheduler is able to reduce the run-time of an MP3 decoder application by 8% compared to a commonly used heuristic scheduler.

show abstract

Data-Parallel Code Generation from Synchronous Dataflow Specification of Multimedia Applications

Cited by 2 publications

References 14 publications

An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee

An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee

Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling

Contact Info

Product

Resources

About