This paper addresses a geometrically invariant watermarking method for digital images. Most previous watermarking algorithms perform weakly against geometric distortions, which desynchronize the location for the inserted watermark. Watermark synchronization, which is a process for finding the location for watermark insertion and detection, is crucial for robust watermarking. In this paper, we propose a watermarking method that is robust to geometric distortions. In order to synchronize the location for watermark insertion and detection, we use circular Hough transform, which extracts circular features that are invariant to geometric distortions. The circular features are then watermarked using additive way on the spatial domain. Our method belongs to the category of blind watermarking techniques, because we do not need the original image during detection. Experimental results support the contention that our method is useful and considerably robust against both geometric distortion attacks and signal processing attacks as listed in Stirmark 3.1.

A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a lowresolution flash ADC is presented. The 3 b MSBs achieved from a flash ADC at every clock save two decision cycles from every SAR ADC channel, resulting in a reduced number of time interleaving channels with a total 27% energy saving compared with the energy consumption of a conventional TI SAR ADC . A prototype 6 b 2 GS/s ADC in a 45 nm CMOS consumes 14.4 mW under a 1.2 V supply and achieves 5.2 ENOB Nyq with a background offset calibration.I. 978-1-4799-0280-4/13/$31.00 c 2013 IEEE

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By taking advantage of the merits of the low power consumption and hardware simplicity of SAR ADCs, 2b/cycle conversion structures in SAR ADCs have been actively studied in recent years for enhanced conversion rates and excellent FoM [1][2][3]. However, many error sources in the 2b/cycle SAR ADCs, such as mismatches between DACs and comparators, and the signal-dependent errors from comparators, namely kickback noise and offset, make it difficult to achieve high resolution. To date, pure 2b/cycle structures operating above hundreds of MS/s have shown a somewhat limited resolution with an ENOB lower than 7 at Nyquist rates [1,2]. As a derivation of the structure, a sub-ADC could be implemented using the 2b/cycle SAR ADC structure for high resolution as in [4], at the cost of increased circuit complexity and static current flow. In this work, we present a resolution-enhancing design technique for 2b/cycle SAR ADCs with negligible hardware overhead, while relieving the requirements for the aforementioned errors: Reconfiguration from a 2b/cycle structure to a normal 1b/cycle SAR ADC with error-correction capability achieves an 8.6 ENOB from a 9b ADC. Figure 26.5.1 shows the circuit diagram of the proposed 2b/cycle SAR ADC core and the concept of the proposed reconfiguration scheme. With two separate DACs, REF-DAC and SIG-DAC [3], the ADC structure saves considerable switching power, 77% and 49.7% from [5] and [1], respectively, in exemplary 8b designs with the same total DAC capacitance. In order to overcome the resolution limitations in a 2b/cycle SAR ADC, the presented ADC reconfigures itself to a normal 1b/cycle SAR ADC for error correction just by disabling the REF-DAC and two comparators. The remaining decision errors induced over the 2b/cycle conversion mode can be corrected as if the entire ADC is a normal 1b/cycle SAR ADC with over-range. The REF-DAC and most of the parts of the SIG-DAC implement the nonbinary 2b/cycle SAR ADC for 9b resolution. Out of the total 279C in each DAC, 24C are utilized for redundancy, which shrinks the effective reference, V REFeff , to 256/279 V REF . The REF-DAC scales down the decision thresholds to +/-128/256, 40/256, 12/256, 4/256, and 1/256 of V REFeff in subsequent order, as decisions proceed from the decision cycle P 1 to P 5 , respectively. The SIG-DAC shifts the residue into a new full range defined by the REF-DAC in each phase. The capacitors in the nonbinary 2b/cycle SIG-DAC have capacitor ratios of 64C-1C with weights (in LSB) of 256, 128, 80, 40, 24, 12, 8, and 4, respectively. The 2b MSBs are determined during P 1 by comparing the sampled input on the SIG-DAC with three references, +/-1/2 V REFeff from the REF-DAC and 0 by COMP 1 . Depending on the results (D 11 D 10 ) of 00, 01, 10, or 11, the SIG-DAC generates a residue by adding +6/8, +2/8, -2/8, or -6/8 V REFeff , respectively, to V IN by controlling two capacitors of 64C and 32C.After five cycles of nonbinary 2b/cycle decisions, the remaining errors induced thus far are corrected with the 1b/cycle reconfiguration...

The goal of the ''2019 Automatic Speaker Verification Spoofing and Countermeasures Challenge'' (ASVspoof) was to make it easier to create systems that could identify voice spoofing attacks with high levels of accuracy. However, model complexity and latency requirements were not emphasized in the competition, despite the fact that they are stringent requirements for implementation in the real world. The majority of the top-performing solutions from the competition used an ensemble technique that merged numerous sophisticated deep learning models to maximize detection accuracy. Those approaches struggle with real-world deployment restrictions for voice assistants which would have restricted resources. We merged skip connection (from ResNet) and max feature map (from Light CNN) to create a compact system, and we tested its performance using the ASVspoof 2019 dataset. Our single model achieved a replay attack detection equal error rate (EER) of 0.30% on the evaluation set using an optimized constant Q transform (CQT) feature, outperforming the top ensemble system in the competition, which scored an EER of 0.39%. We experimented using depthwise separable convolutions (from MobileNet) to reduce model sizes; this resulted in an 84.3 percent reduction in parameter count (from 286K to 45K), while maintaining similar performance (EER of 0.36%). Additionally, we used Grad-CAM to clarify which spectrogram regions significantly contribute to the detection of fake data.